VSC8113
Data Sheet
tTXCLK
TXCLKOUT-
TXCLKOUT+
tSKEW
tSKEW
TXDATAOUT+
TXDATAOUT-
Figure 12. Transmit High-Speed Data Timing Diagram
Table 9. Transmit HIgh-Speed Data Timing (STS-12 Operation)
Symbol
Parameter
Min
Typ
Max
Unit
Condition
t
t
Transmit clock period
1.608
ns
TXCLK
SKEW
Skew between the falling edge of TXCLKOUT+
and valid data on TXDATAOUT
250
ps
Table 10. Transmit High-Speed Data Timing (STS-3 Operation)
Symbol
Parameter
Min
Typ
Max
Unit
Condition
t
t
Transmit clock period
6.43
ns
TXCLK
SKEW
Skew between the falling edge of TXCLKOUT+
and valid data on TXDATAOUT
250
ps
Data Latency
The VSC8113 contains several operating modes, each of which exercise different logic paths through the part. Table
11 bounds the data latency through each path with an associated clock signal.
Table 11. Data Latency
Circuit Mode
Transmit
Description
Clock Reference
TXCLKOUT
RXCLKIN
Range of Clock Cycles
Data TXIN [7:0] to MSB at TXDATAOUT
MSB at RXDATAIN to data on RXOUT[7:0]
4-13
25-35
27-35
2-4
Receive
Equipment Loopback Byte data TXIN [7:0] to byte data on RXOUT[7:0]
Facilities Loopback MSB at RXDATAIN to MSB at TXDATAOUT
TXCLKOUT
RXCLKIN
Clock Recovery Unit
Table 12. Reference Frequency for the CRU
CRUREFCLK Frequency
[MHz]
Output Frequency
[MHz]
CRUREFSEL
STS12
B2
X
B1
X
B0
X
1
1
0
1
0
77.76 ±500ppm
77.76 ±500ppm
622.08
155.52
X
X
X
Uses CMU’s Reference Clock (see Table 13 on page 13)
12 of 22
G52154, Rev 4.5
6/28/02
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