VSC8113
Data Sheet
tPROP
TXLSCKOUT
t
CLKIN
TXLSCKIN
TXIN [7:0]
tINH
tINSU
Figure 9. Transmit Data Input Timing Diagram
Table 4. Transmit Data Input Timing (STS-12 Operation)
Symbol
Parameter
Min
Typ
Max
Unit
Condition
t
t
t
Transmit data input byte clock period
Transmit data setup time with respect to TXLSCKIN
Transmit data hold time with respect to TXLSCKIN
12.86
ns
ns
ns
CLKIN
INSU
INH
1.0
1.0
Maximum allowable propagation delay for connect-
ing TXLSCKOUT to TXLSCKIN
t
t
3.5
ns
ns
PROP
TDT
Data transition to clock falling edge Keep-Out Zone
-2.0
+0.4
Table 5. Transmit Data Input Timing (STS-3 Operation)
Symbol
Parameter
Min
Typ
Max
Unit
ns
Condition
t
t
t
Transmit data input byte clock period
Transmit data setup time with respect to TXLSCKIN
Transmit data hold time with respect to TXLSCKIN
Maximum allowable propagation delay for connect-
12.86
CLKIN
INSU
INH
1.0
1.0
ns
ns
t
1.0
3.2
5.4
ns
(1)
PROP
ing TXLSCKOUT to TXLSCKIN
1. Duty cycle for TXLSCKOUT is 50% ±10% worst-case.
TXIN[7:0]
TXLSCKIN
tTDT
Figure 10. TXLSCKIN Falling Edge Keep-Out Zone
10 of 22
G52154, Rev 4.5
6/28/02
Confidential
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
