VSC8113
Data Sheet
Table 19. Pin Identifications
Pin
Number
Signal
I/O
Level
Description
Facility loopback, loops high-speed receive data and clock directly to
transmit outputs.
1
FACLOOP
I
TTL
2
VDD
CRUEQLP
RESET
LOOPTIM0
B0
Pwr
+3.3V Power Supply
3
I
TTL
TTL
TTL
TTL
TTL
TTL
Loops TXDATAOUT to the CRU replacing RXDATAIN+/-
Resets frame detection, dividers, controls; active HIGH
Enable loop timing operation; active HIGH
Reference clock select, refer to Table 13
Reference clock select, refer to Table 13
Reference clock select, refer to Table 13
+3.3V or +5V power supply for PECL I/Os
Transmit output, high-speed differential data, true
Transmit output, high-speed differential data, complement
Ground
4
I
I
5
6
I
7
B1
I
8
B2
I
9
VDDP
Pwr
O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
TXDATAOUT+
TXDATAOUT-
VSS
PECL
PECL
O
Pwr
O
TXCLKOUT+
TXCLKOUT-
VDDP
PECL
PECL
Transmit high-speed clock differential output, true
Transmit high-speed clock differential output, complement
+3.3V or +5V power supply for PECL I/Os
No connection
O
Pwr
NC
LOSDETEN_
VSS
I
TTL
Enables internal LOS detection, active LOW
Ground
Pwr
RXCLKIN+
RXCLKIN-
VDDP
I
PECL
PECL
Receive high-speed differential clock input, true
Receive high-speed differential clock input, complement
+3.3V or +5V power supply for PECL I/Os
Out of Frame. Frame detection initiated with high level
Disable on-chip clock recovery unit, active HIGH
Receive high-speed differential data input, true
Receive high-speed differential data input, complement
No connection
I
Pwr
OOF
I
I
I
I
TTL
TTL
DSBLCRU
RXDATAIN+
RXDATAIN-
NC
PECL
PECL
NC
No connection
VDD
Pwr
+3.3V Power supply
REFCLKP+
REFCLKP-
VDD
I
I
PECL
PECL
PECL reference clock input, true
PECL reference clock input, complement
+3.3V Power supply
Pwr
NC
No connection
RX50MCK
VSS
O
Pwr
O
TTL
Constant 51.84MHz ref clock output, derived from the CMU
Ground
RXOUT0
RXOUT1
VSS
TTL
TTL
Receive output data bit 0
O
Receive output data bit 1
Pwr
O
Ground
RXOUT2
RXOUT3
TTL
TTL
Receive output data bit 2
O
Receive output data bit 3
17 of 22
G52154, Rev 4.5
6/28/02
Confidential
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
