VSC8113
Data Sheet
t
RXCLKIN
RXCLKIN+
RXCLKIN-
t
RXLSCK
RXLSCKOUT
RXOUT [7:0]
FP
A1
A2
A2
A2
A2
t
RXVALID
Figure 11. Receive Data Output Timing
Table 6. Receive Data Output Timing (STS-12 Operation)
Symbol
Parameter
Min
Typ
Max
Unit
ns
Condition
t
t
Receive clock period
1.608
12.86
RXCLKIN
RXLSCK
Receive data output byte clock period
ns
Time data on RXOUT [7:0] and FP is valid
before and after the rising edge of RXLSCKOUT
t
t
4.0
ns
ns
RXVALID
PW
Pulse width of frame detection pulse FP
12.86
Table 7. Receive Data Output Timing (STS-3 Operation)
Symbol
Parameter
Min
Typ
6.43
Max
Unit
ns
Condition
t
t
Receive clock period
RXCLKIN
RXLSCK
Receive data output byte clock period
51.44
ns
Time data on RXOUT [7:0] and FP is valid
before and after the rising edge of RXLSCKOUT
t
t
22
ns
ns
RXVALID
PW
Pulse width of frame detection pulse FP
51.44
Table 8. PECL/TTL Receive Outputs
Symbol
Parameter
Min
Typ
2
Max
Unit
ns
Condition
10%-90%
10%-90%
20%-80%
20%-80%
t
t
t
t
TTL output rise time
TTL output fall time
PECL output rise time
PECL output fall time
R_TTL
1.5
350
350
ns
F_TTL
ps
R_PECL
F_PECL
ps
11 of 22
G52154, Rev 4.5
6/28/02
Confidential
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
