VSC8113
Data Sheet
Clock Synthesis
The VSC8113 uses an integrated Phase-Locked Loop (PLL) for clock synthesis of the 622MHz high-speed clock
used for serialization in the transmitter section. The PLL is comprised of a Phase-Frequency Detector (PFD), an
integrating operation amplifier and a Voltage Controlled Oscillator (VCO) configured in classic feedback system. The
PFD compares the selected divided-down version of the 622MHz VCO (for pins B0-B2, select divide-by ratios of 8,
12, 16 and 32, see Table 13 on page 13) and the reference clock. The integrator provides a transfer function between
input phase error and output voltage control. The VCO portion of the PLL is a voltage-controlled ring-oscillator with
a center frequency of 622MHz.
The reactive elements of the integrator are located off-chip and are connected to the feedback loop of the amplifier
through the CP1, CP2, CN1 and CN2 pins. The configuration of these external surface-mounted capacitors is shown
in Figure 6 on page 7. Table 1 on page 7 shows the recommended external capacitor values for the configurable
reference frequencies.
Good analog design practices should be applied to the board design for these external components. Tightly controlled
analog ground and power planes should be provided for the PLL portion of the circuitry. The dedicated PLL power
(VDDA) and ground (VSSA) pins should have quiet supply planes to minimize jitter generation within the clock
synthesis unit. This is accomplished by either using a ferrite bead or a C-L-C choke (π filter) on the (VDDA) power
pins. Note: Vitesse recommends a (π filter) C-L-C choke over using a ferrite bead. All ground planes should be tied
together using multiple vias.
The VSC8113 features a Lock Detect function for the CMU, CMULOCKDET. It generates low-going pulses when
the CMU is locked to the incoming REFCLK. This is accomplished by comparing the phase of the synthesized clock
to the reference clock. If the CMULOCKDET output remains HIGH for >10µs, the CMU is locked.
Table 1: Recommended External Capacitor Values
Reference Frequency [MHz]
Divide Ratio
CP
0.1
0.1
0.1
0.1
CN
0.1
0.1
0.1
0.1
Type
X7R
X7R
X7R
X7R
Size
Tolerance
±10%
19.44
38.88
51.84
77.76
32
16
12
8
0603/0803
0603/0803
0603/0803
0603/0803
±10%
±10%
±10%
CP = 0.1µF
CP1
CP2
+
-
CN1
CN2
CN = 0.1µF
Figure 6. External Integrator Capacitor
Reference Clocks
To improve jitter performance and to provide flexibility, an additional differential PECL reference clock input is
provided. This reference clock is internally XNOR’d with a TTL reference clock input to generate the reference for
the CMU. Vitesse recommends using the differential PECL input and tying the unused TTL reference clock LOW. If
7 of 22
G52154, Rev 4.5
6/28/02
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VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
