VSC8113
Data Sheet
D
Q
D
Q
1:8
Serial to
Parallel
0
1
RXOUT[7:0]
RXDATAIN
EQULOOP
RXLSCKOUT
÷ 8
Q
Q
D
D
TXIN[7:0]
TXDATAOUT
8:1
Parallel to
Serial
TXLSCKIN
TXCLKOUT
PLL
÷ 8
TXLSCKOUT
Figure 4. Equipment Loopback Data Path
Split Loopback
Equipment and facility loopback modes can be enabled simultaneously. In this case, high-speed serial data received
(RXDATAIN) and received/recovered clock are Mux’d through to the high-speed serial outputs (TXDATAOUT) and
(TXCLKOUT). The low-speed transmit byte wide bus (TXIN[7:0]) and (TXLSCKIN) are Mux’d into the low-speed
byte wide receive output bus (RXOUT[7:0]) and (RXLSCKOUT). See Figure 5.
D
Q
D
Q
1:8
Serial to
Parallel
RXOUT[7:0]
RXDATAIN
CRU
Recovered
Clock
0
1
RXLSCKOUT
TXIN[[7:0]
RXCLKIN
DSBLCRU
TXDATAOUT
Q
D
Q
D
8:1
Parallel to
Serial
TXCLKOUT
TXLSCKIN
Figure 5. Split Loopback Data Path
Loop Timing
LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted HIGH. In this mode, the CMU is
bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single external
source.
LOOPTIM1 mode bypasses the REFCLK input and uses the divide-by-8 version of the receive clock as the reference
input to the CMU. This mode is selected by asserting the LOOPTIM1 input HIGH. The part is forced out of this
mode if it is in the LOS state or in Equipment Loopback to prevent the CMU from feeding its own clock back.
6 of 22
G52154, Rev 4.5
6/28/02
Confidential
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
