VSC7216-02
Data Sheet
RECEIVER FUNCTIONAL DESCRIPTION
Serial Data Source
Each receive channel has both primary and redundant serial input ports, PRXn and RRXn, respectively, that consist of
differential PECL input buffers. Each channel also has a control input, RXP/Rn, used to select either the primary or
redundant serial input as the data source for that channel. For example, when RXP/RC is HIGH, the C channel serial
data source is PRXC. When LBENn[1:0] = 10, the channel’s transmitter is looped back and becomes the serial data
source regardless of the state of RXP/Rn (see Table 5).
Table 5. Serial Data Source Selection
LBENn[1:0]
≠ 1 0
RXP/Rn
Serial Data Source
RRXn
0
1
≠ 1 0
PRXn
LBTXn
Loopback from transmitter
= 1 0
X
Signal Detection
Each channel’s primary and redundant PECL input buffers have an associated signal detect output, PSDETn and
RSDETn. All eight outputs are available for continuous monitoring of both the selected and non-selected input. Each
signal detect output is asserted HIGH when transitions are detected on the associated PECL input and the signal
amplitude exceeds 200mV. A LOW indicates that either no transitions are detected or the signal amplitude is below
50mV. The signal detect outputs are considered undefined when the signal amplitude is in the 50mV to 200mV range.
The signal detect circuitry behaves like a re-triggerable one shot that is triggered by signal transitions, and whose
time-out interval ranges from 40 to 80 bit times. The transition density is not checked to make sure that it corresponds
to a valid Fibre Channel data stream. The PSDETn and RSDETn output timing is identical to the low-speed receiver
outputs, as selected by RMODE[1:0] in Table 6 on page 11.
Receiver Equalization
Incoming data on the PRX/RRX inputs typically contains a substantial amount of Inter Symbol Interference (ISI) or
deterministic jitter that reduces the ability of the receiver to recover data without errors. An equalizer has been added
to each of the receiver’s input buffers in order to compensate for this deterministic jitter. This circuit has been
designed to effectively reduce the ISI commonly found in copper cables or backplane traces due to low frequencies
traveling faster than high frequencies as a result of the skin effect. The equalizer boosts high frequency edge response
in order to reduce the adverse effects of ISI. Receiver equalization is ON by default and can be disabled on each
channel individually through the JTAG interface. Power-on resets receiver equalization to its default state.
Serial Input Termination Value
The VSC7216-02 features user controllable on-chip terminations for all high-speed serial PECL inputs. The on-chip
input termination value is controllable by means of the RREF pin. A single external reference resistor, when
connected between RREF and ground, will control the value of differential input resistance for all channels. The
range of control is between values of 100Ω and 150Ω for the differential input resistance. The ratio of external RREF
resistance to PECL termination resistance is 10:1. For example, to obtain a differential input termination resistance of
9 of 40
G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
