VSC7216-02
Data Sheet
The term “word clock” will be used for whichever clock, REFCLK, RCLKA/RCLKNA or RCLKn/RCLKNn is
selected as the output timing reference. If RMODE[1] is HIGH, each channel’s RCLKn/RCLKNn outputs are
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complementary outputs at 1/10 or 1/20 the baud rate of the incoming data depending upon DUAL. When RCLKA/
RCLKNA is selected as the output timing reference, the Channel B, C and D RCLKn/RCLKNn outputs are copies of
RCLKA/RCLKNA. If RMODE[1] is LOW, then each channels’ RCLKn/RCLKNn outputs are held in a LOW/HIGH
state, respectively, and the data and status outputs are timed to REFCLK. If DUAL is HIGH, all data at the four output
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ports are synchronously clocked out on both positive and negative edges of the selected word clock at 1/20 the baud
rate. If DUAL is LOW, the data is clocked out of the VSC7216-02 only on the rising edge of the selected word clock
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at 1/10 the baud rate. Timing waveforms for the output data and status are shown in Figure 8, Figure 9 and Figure
10.
REFCLK
(DUAL = 0)
REFCLK
(DUAL = 1)
Rn[7:0]
IDLEn
KCHn
ERRn
Valid
Valid
Valid
Figure 8. Receive Timing, RMODE[1:0] = 00
REFCLK
(DUAL = 0)
REFCLK
(DUAL = 1)
Rn[7:0]
IDLEn
KCHn
ERRn
Valid
Valid
Valid
Figure 9. Receive Timing, RMODE [1:0] = 01
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G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
