VSC7216-02
Data Sheet
Figures 2, 3, and 4 show possible relationships between data and control inputs and the selected input timing source.
Figure 2 shows how REFCLK is used as an input timing reference. Figure 3 and Figure 4 show how TBCn is used as
an input timing reference. When TBCn is used to define a data eye, as shown in Figure 4, it functions as an additional
data input that simply toggles every cycle.
The REFCLK and TBCn inputs are not used directly to clock the input data. Instead, an internal PLL generates edges
aligned with the appropriate clock. The arrows on the rising edges of these signals define the reference edge for the
th
internal phase detection logic. An internal clock is generated at 1/10 the serial transmit data rate that is locked to the
selected input timing source. This is especially important when DUAL is HIGH and input timing is referenced to
REFCLK since the falling edge is not used. In this mode, the internal clock’s rising edges are placed coincident with
REFCLK’s rising edges, halfway between REFCLK’s succeeding rising edges.
A similar situation exists when TBCn is used to define a data eye, only the rising edges of TBCn are used to define
the external data timing. The internal clock active edges are placed at 90° and 270° points between consecutive TBCn
rising edges (which are assumed to be 360° apart).
REFCLK
(DUAL = 0)
REFCLK
(DUAL = 1)
Tn[7:0]
C/Dn
Valid
Valid
Valid
WSENn
Figure 2. Transmit Timing, TMODE[2:0] = 000
TBCA
or
TBCn
Tn[7:0]
C/Dn
Valid
Valid
Valid
WSENn
Figure 3. Transmit Timing, TMODE[2:0] = 10x
0°
90°
180°
270°
360°
TBCA
or
TBCn
Tn[7:]
C/Dn
Valid
Valid
Valid
WSENn
Figure 4. Transmit Timing, TMODE[2:0] = 11x (ASIC-Friendly TIming)
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G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
