VSC7216-02
Data Sheet
State Machine status and FIFO error status, to produce the prioritized per-character link status output information (see
Table 9 on page 18).
Elastic Buffer and Channel Deskewing
Elastic buffers are included in each of the four receive channels. Decoded data and status information are written into
these buffers on each channel’s recovered clock and are read on the selected output clock. In addition to allowing
decoded data to easily cross from a channel’s recovered clock domain to its output clock domain, the elastic buffers
facilitate two other functions. Through inter-channel deskewing they allow channel alignment (the reconstruction of a
multi-byte word as presented to the transmitting devices). They also facilitate rate matching through IDLE character
insertion/deletion when the channel’s recovered clock is not frequency-locked to its output clock.
The VSC7216-02 supports three levels of inter-channel deskewing through setting the RXFIFO0 and RXFIFO1 pins.
The amount of deskewing selected directly affects the receiver latency and word alignment capability of the device.
The user is thus enabled to determine the optimum trade-off between deskewing, latency and word alignment for the
particular application. The relationship between these parameters is detailed in “Word Alignment” on page 14.
There are three conditions under which a receive channel’s elastic buffer is recentered. The RESETN input, when
asserted, recenters the read/write pointers in each elasticity buffer. Whenever a comma character is received that
changes the receive character’s framing boundary, the elasticity buffer is recentered. Lastly, it is also recentered
whenever the receiver detects the synchronization point in the Word Sync Sequence. All three of these events are
associated with chip initialization or link initialization and would not occur during normal data transfer. Note that
recentering can result in the loss or duplication of decoded character data and status information.
When a condition changes transmit timing (for example, phase shifts in TBC) or shifts phase/alignment into the
receiver, the user should initiate a Word Sync Event to recenter all elasticity buffers. Otherwise, data corruption could
occur.
The VSC7216-02 presents recovered data on Rn[7:0] and status on IDLEn, KCHn and ERRn. These outputs are
timed either to each channel’s own recovered clock (RCLKn/RCLKNn), to Channel A’s recovered clock (RCLKA/
RCLKNA), or to REFCLK. The output timing reference is selected by RMODE[1:0] (see Table 6). The transmitter
input skew buffer error outputs TBERRn and the analog signal detect outputs PSDETn and RSDETn are also
synchronized to the selected output timing reference. There are two choices for REFCLK-based timing that differ in
the positioning of the data valid window associated with the output signals timed to REFCLK; when
RMODE[1:0] = 00, REFCLK is approximately centered in the output data valid window, and when
RMODE[1:0] = 01, REFCLK slightly leads the data valid window so that output data appears to have a more typical
“Clock-to-Q” timing relationship to REFCLK.
Table 6. Receiver Interface Output Timing Mode
RMODE[1:0]
Output Timing Reference
REFCLK (Centered)
REFCLK (Leading)
RCLKA/RCLKNA
0 0
0 1
1 0
1 1
RCLKn/RCLKNn
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G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
