VSC7216-02
Data Sheet
RCLKn
(DUAL = 0)
RCLKn
(DUAL = 1)
Rn[7:0]
IDLEn
KCHn
ERRn
Valid
Valid
Valid
Figure 10. Receive Timing, RMODE[1:0] = 1x
The data coming from the decoder is clocked into the elastic buffer by the recovered clock from the channel’s CRU.
The data is clocked out of the elastic buffers with word clock. If the transmitting device’s REFCLK is not precisely
frequency-locked to a receive channel’s word clock, the channel’s elastic buffer will tend to gradually fill or empty as
the recovered clock (which is by definition frequency-locked to the transmitter’s REFCLK) steadily drifts in phase
relative to the word clock.
In order to accommodate frequency differences between a transmitter’s REFCLK and the word clock, the
VSC7216-02 can automatically perform rate matching by either deleting or duplicating IDLE characters. The
FLOCK input must be LOW to enable rate matching which, based on how the WSI input is connected, can either be
performed in each channel individually or can be performed in parallel across a group of channels that are
word-aligned. This is discussed in detail in the following section describing Word Alignment. It is the user’s
responsibility to ensure that the frequency at which IDLEs are simultaneously transmitted on each channel
accommodates the frequency differences, if any, in their system architecture. Not meeting the IDLE density
requirements could result in Underrun/Overrun Errors. However, the use of a continuous stream of IDLE characters
should be avoided when rate matching is enabled. The IDLE addition/deletion logic relies on the status bits (see Table
9 on page 18 for details) to identify K28.5 IDLE characters. The use of continuous IDLE characters will force the
VSC7216-02 into the RESYNC state (see Figure 11 on page 17 for details), resulting in a status bit sequence that the
addition/delection logic does not recognize as an IDLE character.
The elastic buffer is designed to allow a maximum phase drift of 2 serial clock bit times (RXFIFO[0:1] = 01) and
5 serial clock bit times (RXFIFO[0:1] = 00 or 11) between re-synchronizations, which sets a limit on the maximum
data “packet” length allowed between IDLEs. This maximum packet length depends on the frequency difference
between the transmitting and receiving devices REFCLKs. Let Δφ represent phase drift in bit times, and let 2π
represent one full 10-bit character of phase drift. Limiting phase drift to five bit times means the following inequality
must be satisfied (similar equations hold for 2 bit times of drift):
Δφ ≤ ((0.5) × 2π)
(EQ 1)
Let L be the number of 10-bit characters transmitted, and let Δf be the frequency offset in ppm. The total phase drift in
bit times is given by:
6
Δφ = (Δf ⁄ 10 ) × 2πL
(EQ 2)
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G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
