VSC7216-02
Data Sheet
100Ω, use an external resistor of 1kΩ (1%). If no impedance-setting resistor is used, it is recommended the RREF pin
be connected to V . In this configuration, the value of input termination resistance is very high and is essentially an
DD
open circuit. If the RREF pin is connected to V , external termination is required for each PECL input.
DD
Placing the single external resistor physically close to the VSC7216-02 RREF pin is not required. RREF is a global
configuration pin affecting the primary and redundant PECL inputs for all four channels.
Clock and Data Recovery
At the receiver, each channel contains an independent Clock Recovery Unit (CRU) that accepts the selected serial
input source, extracts the high-speed clock and retimes the data. Each CRU automatically locks on data and if the data
is not present, will automatically lock to the REFCLK. This maintains a very well behaved recovered clock, RCLKn/
RCLKNn does not contain any slivers and will operate at a frequency of the REFCLK reference 200ppm. The use
of an external Lock-to-Reference pin is not needed.
The CRU must perform bit synchronization that occurs when the CRU locks onto and properly samples the incoming
serial data as described in the previous paragraph. When the CRU is not locked onto the serial data, the 10-bit data out
of the decoder is invalid, which results in numerous 8B/10B decoding errors or disparity errors. When the link is
disturbed (for example, the cable is disconnected or the serial data source is switched), the CRU will require a certain
amount of time to lock onto data, which is specified in “Data Acquisition Lock Time” in Table 18, "General Receive
AC Characteristics" on page 26.
Deserializer and Character Alignment
The retimed serial data stream is converted into 10-bit characters by the deserializer. A special 7-bit “comma” pattern
(0011111xxx or 1100000xxx) is recognized by the receiver and allows it to identify the 10-bit character boundary.
Note that this pattern is found in three special characters, K28.1, K28.5 and K28.7, however, K28.5 is chosen as the
unique IDLE character. Only K28.1 and K28.5 should be used in normal operation. The K28.7 character should be
reserved for test and characterization use.
Character alignment occurs when the deserializer synchronizes the 10-bit character framing boundary to a comma
pattern in the incoming serial data stream. If the receiver identifies a comma pattern in the incoming data stream that
is misaligned to the current framing boundary the receiver will re-synchronize the recovered data in order to align the
data to the new comma pattern. Resynchronization ensures that the comma character is output on the internal 10-bit
bus so that bits 0 through 9 equal 0011111xxx or 1100000xxx. If the comma pattern is aligned with the current
framing boundary, resynchronization will not change the current alignment. Resynchronization is always enabled and
cannot be turned off when ENDEC is HIGH. After character resynchronization the VSC7216-02 ensures that within a
link, the 8-bit data sent to the transmitting VSC7216-02 will be recovered by the receiving VSC7216-02 in the same
bit locations as the transmitter (i.e., Tn[7:0] = Rn[7:0]). When ENDEC is LOW, Comma detection and alignment are
enabled only if KCHAR is HIGH.
10B/8B Decoder
The 10-bit character from the deserializer is decoded in the 10B/8B decoder, which outputs the 8B data byte and three
bits of status information. If the 10-bit character does not match any valid value, an out-of-band error is generated,
which is output on the receiver status bus. Similarly, if the running disparity of the character does not match the
expected value, a disparity error is generated. The decoder also reports when a K-character is received, and
distinguishes the K28.5 (IDLE) character from other K-characters. This status information is combined with LOS
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G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
