VSC7216-02
Data Sheet
Table 23. Pin Identifications (continued)
Pin
Name
I/O
Type
Description
4N
4M
4J
PTXENA
PTXENB
PTXENC
PTXEND
I
TTL
Primary TX Output Enable for Channel n. When HIGH PTXn+/- is active, when
LOW PTXn+/- is powered down and the outputs are undriven.
4H
3P
3N
3H
3G
RTXENA
RTXENB
RTXENC
RTXEND
I
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Redundant TX Output Enable for Channel n. When HIGH RTXn+/- is active,
when LOW RTXn+/- is powered down and the outputs are undriven.
18P, 19R
20U, 20V
17R, 19U
20W, 18T
RA[7:0]
RB[7:0]
RC[7:0]
RD[7:0]
O
O
O
O
O
O
O
O
Receive Data for Channel A. Synchronous to RCLKA/RCLKNA or REFCLK as
selected by RMODE[1:0].
15V, 15U
18Y, 17Y
15W, 14U
16Y, 13V
Receive Data for Channel B. Synchronous to RCLKB/RCLKNB or REFCLK as
selected by RMODE[1:0].
16C, 15C
15D, 18A
17A, 15B
14D, 16A
Receive Data for Channel C. Synchronous to RCLKC/RCLKNC or REFCLK as
selected by RMODE[1:0].
20E, 18G
17G, 19F
20C, 17F
19D, 20B
Receive Data for Channel D. Synchronous to RCLKD/RCLKND or REFCLK as
selected by RMODE[1:0].
17N
18W
17C
19H
IDLEA
IDLEB
IDLEC
IDLED
Idle Detect for Channel n. When HIGH, an IDLE character has been detected
by the decoder and is on Rn[7:0].
When ENDEC = LOW, this is equivalent to COMDETn.
19P
16V
16D
18H
KCHA
KCHB
KCHC
KCHD
Kxx.x Character Detect for Channel n. When HIGH, a special Kxx.x character
has been detected by the decoder and is on Rn[7:0].
When ENDEC = LOW, this is equivalent to data bit Rn8.
18N
16U
20A
20F
ERRA
ERRB
ERRC
ERRD
Error Detect for Channel n. When HIGH, an invalid 10-bit character or disparity
error has been detected and the data on Rn[7:0] is invalid.
When ENDEC = LOW, this is equivalent to data bit Rn9.
20M
19M
17T
20Y
18E
17E
17K
18K
RCLKA
RCLKNA
RCLKB
RCLKNB
RCLKC
RCLKNC
RCLKD
RCLKND
Recovered Clock Outputs for Channel n. These outputs are driven from either
the channel A or channel n recovered clock, at 1/10th or 1/20th the baud rate,
as selected by RMODE[1:0] and DUAL. When unused and REFCLK is
selected as the output timing reference, RCLKn is LOW and RCLKNn is HIGH.
6U
4W
RMODE0
RMODE1
I
I
TTL
Receive Output Data Timing Mode. Determines the timing reference for all
receive channels’ Rn[7:0], IDLEn, KCHn and ERRn output data, and also for
the PSDETn, RSDETn and TBERRn outputs, as defined in Table 6 on page
11.
1U, 2U
1Y, 2Y
1A, 2A
1D, 2D
PRXA+/-
PRXB+/-
PRXC+/-
PRXD+/-
PECL
Primary Differential Serial Rx Inputs for Channel n. These pins receive the
serialized input data when LBENn[1] is LOW (see Table 5 on page 9 and Table
10 on page 19) and RXP/Rn is HIGH. AC-coupling is recommended.
32 of 40
G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
