VSC7216-02
Data Sheet
Table 23. Pin Identifications (continued)
Pin
Name
I/O
Type
Description
17L
WSO
O
TTL
Word Sync Output. Used to set initial channel word alignment, and to maintain
alignment by controlling IDLE character insertion/deletion as defined in Table 8
on page 15.
15A
13B
14A
19K
13A
TCK
TMS
I
I
TTL
TTL
TTL
TTL
TTL
JTAG Test Access Port Test Clock Input.
JTAG Test Access Port Test Clock Input.
JTAG Test Access Port Test Clock Input.
JTAG Test Access Port Test Data Output.
TDI
I
TDO
O
I
TRSTN
JTAG Test Access Port Test Logic Reset Input. RESETN will also reset JTAG
registers, including signal pre-emphasis, reduced PECL output swing and
cable equalization, to their default states. If JTAG is not used, connect to
ground through a 1kΩ resistor.
14Y
13Y
CREG
RATE
Analog Capacitor for Internal Voltage Regulation. Connect a 4.7µF or larger capacitor
between this pin and GND.
I
TTL
Rate Mode. When HIGH, VSC7216-02 runs at full data rate. When LOW,
half-speed data rate is selected.
6V
8V
TEST0
RREF
N/A
Reserved for Factory Test. Tie to VSSD during normal operation.
Analog Resistor Reference. The resistor value (1%) placed between RREF and GND
controls the value of input resistance for all high-speed PECL inputs. See
“Serial Input Termination Value” on page 9.
20N
17H
RXFIFO0
RXFIFO1
I
TTL
Used to Control the Amount of Inter-channel Skew that can be corrected. The
receiver latency and word alignment capabilities are also affected by these
settings. See Table 7 on page 14.
2L, 4L
VDDA
Pwr
2.5V Analog Power Supply to PLL. Should be filtered with a ferrite bead and
decoupling capacitors to VSSA.
2K, 4K
VSSA
VDDD
Pwr
Pwr
Analog Ground to PLL.
11B, 11Y,
13D, 15Y,
1C, 1V,
Digital Power Supply, 2.5V.
20K, 3L,
4D, 4U,
5C, 5V
11A, 13C,
13U, 19L,
3C, 3K, 3V,
4C, 4E, 4T,
4V, 7A,
VSSD
VDDT
Pwr
Pwr
Digital Ground
7C, 8W
14B, 14W,
17B, 17D,
17P,
TTL Output Power Supply, 2.5V or 3.3V.
17U, 17W,
18L, 19B,
19E, 19G,
19J, 19N,
19T, 19W
34 of 40
G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
