VSC7216-02
Data Sheet
Table 23. Pin Identifications (continued)
Pin
Name
I/O
Type
Description
1W, 2W
3Y, 4Y
3A, 4A
1B, 2B
RRXA+/-
RRXB+/-
RRXC+/-
RRXD+/-
I
PECL
Redundant Differential Serial Rx Inputs for Channel n. These pins receive the
serialized input data when LBENn[1] is LOW (Table 5 on page 9 and Table 10
on page 19) and RXP/Rn is LOW. AC-coupling is recommended.
4P
3T
4R
3U
4F
3D
4G
3E
LBENA0
LBENA1
LBENB0
LBENB1
LBENC0
LBENC1
LBEND0
LBEND1
I
TTL
Loop Back Enable for Channel n. These inputs control the channel serial or
parallel loopback configuration as described in Table 10 on page 19.
2V
3W
3B
2C
RXP/RA
RXP/RB
RXP/RC
RXP/RD
I
TTL
Rx Input Primary/Redundant Serial Input Select for Channel n. When
LBENn(1) is LOW (see Table 5 on page 9 and Table 10 on page 19):
HIGH on RXP/Rn selects PRXn serial input;
LOW on RXP/Rn selects RRXn serial input
20P
19V
18D
17J
PSDETA
PSDETB
PSDETC
PSDETD
O
O
I
TTL
TTL
Primary Analog Signal Detect, Channel n. This output goes HIGH when the
amplitude on PRXn is greater than 200mV, LOW when the input is less than
50mV. PSDETn is not defined when the input is between 50mV and 200mV.
Output timing is same as Rn[7:0].
17M
18U
19C
20J
RSDETA
RSDETB
RSDETC
RSDETD
Redundant Analog Signal Detect, Channel n. This output goes HIGH when the
amplitude on RRXn is greater than 200mV, LOW when the input is less than
50mV. RSDETn is not defined when the input is between 50mV and 200mV.
Output timing is same as Rn[7:0] .
8A
9D
REFCLKP
REFCLKN
PECL
REFCLK Differential Positive and Negative PECL or Single-Ended TTL Inputs.
This rising edge of this clock latches transmit data and control into the input
register. It also provides the reference clock, at 1/10th or 1/20th of the baud rate
to the PLL as selected by DUAL. For PECL, connect both REFCLKP and
REFCLKN. If TTL, connect to REFCLKP, and terminate REFCLKN with a
0.1uF capacitor to ground and 50Ω pull-up and pull-down biasing resistors.
See Figure 25 on page 27.
1K
1L
CAP0
CAP1
Analog Loop Filter Capacitor for Clock Generation PLL. These pins must be properly
connected to external capacitors, typically 0.1µF. See “Clock Synthesizer” on
page 3 and Figure 1 on page 3 for more details.
5U
DUAL
I
I
TTL
Dual Clock Mode. When LOW, REFCLK and RCLKn/RCLKNn are 1/10th the
baud rate. When HIGH, they are 1/20th the baud rate.
13W
FLOCK
TTL
Frequency-Locked Mode. When HIGH, each transmit channel’s REFCLK is
frequency-locked to the receive channel’s word clock. When LOW, rate
matching may be enabled, but is also dependent on WSI input per Table 8 on
page 15.
12D
BIST
I
TTL
Built-In Self Test Mode. When HIGH, all transmit channels continuously send a
256 byte incrementing data pattern, and all receive channels signal correct
reception of the test pattern with a LOW on the TBERRn outputs. When LOW,
BIST mode is disabled.
12V
12U
20L
ENDEC
RESETN
WSI
I
I
I
TTL
TTL
TTL
Encoder/Decoder Enable. When HIGH the VSC7216-02 is configured for 8-bit
operation, internal 8B/10B encoding is enabled. When LOW, a 10-bit interface
is used, internal 8B/10B encoding is bypassed.
RESETN Input. When asserted LOW, the transmitter input skew buffers and
receiver elastic buffers are recentered and all JTAG registers set to the default
state.
Word Sync Input. Used to control channel alignment and IDLE character
insertion/deletion as defined in Table 8 on page 15.
33 of 40
G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
