VSC7216-02
Data Sheet
A simple expression for maximum packet length as a function of frequency offset is derived by substituting (2) in (1)
and solving for L:
6
L ≤ (0.5 × 10 ) ⁄ Δf
(EQ 3)
As an example, if the frequency offset is 200ppm, then the maximum packet length should not be more than 2.5 K
bytes. To increase the maximum packet length L, decrease the frequency offset Δf. Please note that if only one K28.5
is transmitted between “packets” of data, it might be dropped during compensation for phase drift. If the user must
have at least one K28.5 between these two packets then two K28.5s must be transmitted.
Word Alignment
The VSC7216-02 performs channel-to-channel word alignment. In this mode of operation, if the data from all four
channels on the transmitting VSC7216-02 (for example, the 4 Tn[7:0] busses) is viewed as a 32-bit word, the
receiving VSC7216-02 will recover an identical word. For example, if a transmit pattern was “ABCD”, “EFGH”,
“IJKL”, and so forth, the receiver should not recover data words as “ABGD”, “EFKH”, “IJOL”, and so on. This
requires the four transmit channels to obtain input data on a common clock (for example, TMODE[2:0] = 000 or
1X0) and the four receive channels to present output data on a common word clock (for example, RMODE[1:0] = 0X
or 10).
Within the receiver there are elastic buffers used to deskew the four channels and align them to a common word clock.
An elastic buffer allows the channels’ input to be skewed up a selectable number of bit times in order to accommodate
circuit imperfections, differences in transmission delay and jitter. Three levels of deskewing are possible and the
desired level is set with the RXFIFO0 and RXFIFO1 pins. The receiver latency and the ability to perform chip-to-chip
word alignment are also affected by these settings. These relationships are shown in Table 7.
Table 7. Effects of RXFIFO0 and RXFIFO1 Settings
RLA
(Min)
RLAT
(Max)
Max Deskew
(Bit Times)
RXFIFO0
RXFIFO1
Word Alignment
Supports intra-chip and
multi-chip alignment
0
1
12
See Table 18
See Table 18
See Table 18
See Table 18
See Table 18
See Table 18
Supports intra-chip and
multi-chip alignment
0
0
40 (typ)
90 (typ)
Supports intra-chip but not
multichip alignment
1
1
1
0
RSVD
1. ENDEC = 1, Recenter only.
2. ENDEC = X, Recenter + Drift.
When RXFIFO[0:1] = 01 or 00, multiple VSC7216-02 devices can also be used in synchronous operation if the skew
between all serial input pairs is maintained less than 12 or 40 serial clock bit times, respectively. In order to perform
14 of 40
G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
