欢迎访问ic37.com |
会员登录 免费注册
发布采购

VSC7212RG 参数 Datasheet PDF下载

VSC7212RG图片预览
型号: VSC7212RG
PDF下载: 下载PDF文件 查看货源
内容描述: 千兆互连芯片 [Gigabit Interconnect Chip]
分类和应用:
文件页数/大小: 34 页 / 505 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
 浏览型号VSC7212RG的Datasheet PDF文件第25页浏览型号VSC7212RG的Datasheet PDF文件第26页浏览型号VSC7212RG的Datasheet PDF文件第27页浏览型号VSC7212RG的Datasheet PDF文件第28页浏览型号VSC7212RG的Datasheet PDF文件第30页浏览型号VSC7212RG的Datasheet PDF文件第31页浏览型号VSC7212RG的Datasheet PDF文件第32页浏览型号VSC7212RG的Datasheet PDF文件第33页  
VITESSE  
SEMICONDUCTOR CORPORATION  
Preliminary Data Sheet  
Gigabit Interconnect Chip  
VSC7212  
Table 16: Pin Identification  
Pin  
Name  
I/O  
Type  
Pin Description  
Transmit data, synchronous to REFCLK or TBC.  
99,98,97  
96,95,91  
90,89  
T0, T1, T2  
T3, T4, T5  
T6, T7  
I
TTL  
Control/Data. If KCHAR=C/D=LOW, then T(7:0) is used to generate  
transmit data. If KCHAR=C/D=HIGH then special Kxx.x characters are  
transmitted based upon the value of T(7:0). If KCHAR=LOW and C/D  
=HIGH, IDLE characters are transmitted.  
88  
C/D  
I
TTL  
When ENDEC=LOW, this is equivalent to data bit T8.  
Word Sync ENable. Asserted HIGH for one cycle to initiate transmission of  
the Word Sync Sequence as defined in Figure 5 and related text.  
When ENDEC=LOW, this is equivalent to data bit T9.  
87  
92  
WSEN  
TBC  
I
I
TTL  
TTL  
Transmit Byte Clock. Optional input data timing reference for T(7:0),  
WSEN and C/D.  
Special Kxx.x CHARacter Enable. When C/D is HIGH, KCHAR controls  
data sent to the transmitter. When LOW, IDLE characters are sent. When  
HIGH, Kxx.x special characters are sent as encoded on T(7:0). This is  
intended to be a static input and cannot be changed on a cycle-by-cycle  
basis.  
86  
KCHAR  
I
TTL  
When ENDEC=LOW, this is equivalent to ENCDET. A HIGH enables  
comma detection and alignment. A LOW disables both.  
85  
82  
81  
TMODE0  
TMODE1  
TMODE2  
Transmit Input Data Timing MODE. Determines the timing reference for  
T(7:0), WSEN and C/D as defined in Table 1.  
I
TTL  
TTL  
Transmit Buffer ERRor. When HIGH indicates that the elastic limit of the  
transmit input skew buffer was exceeded, output timing is same as R(7:0). A  
LOW indicates correct reception of the 256-byte incrementing pattern in  
BIST mode.  
73  
TBERR  
O
4
5
PTX+  
PTX-  
Primary Differential Serial TX Output. These pins output serialized  
transmit data when PTXEN is HIGH. AC-coupling is recommended.  
O
O
I
PECL  
PECL  
TTL  
9
10  
RTX+  
RTX-  
Redundant Differential Serial TX output. These pins output serialized  
transmit data when RTXEN is HIGH. AC-coupling is recommended.  
Primary TX Output ENable. When HIGH, PTX+/- is active, when LOW  
PTX+/- is powered down and the outputs are un-driven.  
2
7
PTXEN  
RTXEN  
Redundant TX Output ENable. When HIGH RTX+/- is active, when LOW  
RTX+/- is powered down and the outputs are un-driven.  
I
TTL  
46,48,52  
53,55,56  
58,60  
R0, R1, R2  
R3, R4, R5  
R6, R7  
Receive Data. Synchronous to RCLK/RCLKN or REFCLK as selected by  
RMODE(1:0).  
O
O
O
TTL  
TTL  
TTL  
IDLE Detect. When HIGH, an IDLE character has been detected by the  
decoder and is on R(7:0)  
When ENDEC=LOW, this is equivalent to COMDET.  
68  
65  
IDLE  
KCH  
Kxx.x CHaracter Detect. When HIGH, a special Kxx.x character has been  
detected by the decoder and is on R(7:0).  
When ENDEC=LOW, this is equivalent to data bit R8.  
© VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012  
Tel: (800)-VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com  
Internet: www.vitesse.com  
G52268-0, Rev 3.3  
04/10/01  
Page 29  
 复制成功!