Advance Product Information
Subject to Change
VSC7111 Datasheet
Registers
3.4.4
Global Input State
This register defines the input enable and termination settings for all inputs.
Register 54’h: Global Input State
Table 29.
Bit Name
Access Description
Default
7
6
Unused
R/W
R/W
Unused
0
0
GLOWPWR_OVRD
Allow register control of input buffer bandwidth
control
1: GINPLOW_PWR register controls the input
buffer bandwidth/power
0: LOWPWR pin controls the input buffer
bandwidth/power
5:4 Unused
R/W
R/W
Unused
00
00
3:2 GINPLOW_PWR
Input bandwidth control
11: Maximum power/bandwidth operation when
GLOWPWR_OVRD = 1
00: Minimum power/bandwidth operation when
GLOWPWR_OVRD = 1
1
0
GINPTERMVDD
GINPPOWEROFF
R/W
R/W
Terminate to VDD
1: Low input common-mode termination
impedance to VDD
0: High input common-mode termination
impedance to VDD (~1 kΩ when input buffer is
enabled, > 50 kΩ when disabled)
0
1
Global input power off
1: Power off all inputs
0: Power on all inputs
3.4.5
Global Input LOS
This register configures the LOS threshold value for all inputs.
Table 30.
Register 55’h: Global Input LOS
Bit Name
Access Description
Default
7
GLOSON
R/W
R/W
Global LOS on
1: LOS on
0: LOS off
1
6:0 GINPLOS
Global LOS threshold settings
1111111: ~300 mV (maximum)
…
1100000
0111111: ~30 mV (minimum useful value)
0111101: 0 mV (minimum)
0111100: Unsupported
Revision 2.0
September 2010
Confidential
Page 36
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
