Advance Product Information
Subject to Change
VSC7111 Datasheet
Contents
Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
MUX Settings ............................................................................................ 12
Static Mode Mapping .................................................................................. 13
Input EQ Static Mode Settings ..................................................................... 13
Output EQ Static Mode Settings ................................................................... 14
Power State of Inputs and Outputs in Static Mode .......................................... 14
Master Mode Address Mapping for EEPROM.................................................... 16
Register Map, Individual Registers................................................................ 25
Global Programming................................................................................... 26
Register Map, Global Registers..................................................................... 26
Table 10. Page 00’h: Reserved................................................................................... 28
Table 11. Page 10’h: Input Gain 1.............................................................................. 28
Table 12. Page 11’h: Input Gain 2.............................................................................. 28
Table 13. Page 13’h: Input State................................................................................ 29
Table 14. Page 14’h: Input LOS ................................................................................. 29
Table 15. Page 15’h: Input AEQ Control ...................................................................... 30
Table 16. Page 16’h: Input ISE 1 Long........................................................................ 30
Table 17. Page 17’h: Input ISE 1 Short....................................................................... 31
Table 18. Page 18’h: Input ISE 2 Long........................................................................ 31
Table 19. Page 19’h: Input ISE 2 Short....................................................................... 31
Table 20. Page 20’h: Output PE 1............................................................................... 31
Table 21. Page 21’h: Output PE 2............................................................................... 32
Table 22. Page 22’h: Output Level.............................................................................. 32
Table 23. Page 23’h: Output Mode ............................................................................. 33
Table 24. Page 2E’h: PCIe Control.............................................................................. 34
Table 25. Page F0’h: Channel Status .......................................................................... 34
Table 26. Register 50’h: Global MUX Select ................................................................. 35
Table 27. Register 51’h: Global Input Gain 1................................................................ 35
Table 28. Register 52’h: Global Input Gain 2................................................................ 35
Table 29. Register 54’h: Global Input State ................................................................. 36
Table 30. Register 55’h: Global Input LOS................................................................... 36
Table 31. Register 56’h: Global Output PE 1 ................................................................ 37
Table 32. Register 57’h: Global Output PE 2 ................................................................ 37
Table 33. Register 58’h: Global Output Level ............................................................... 37
Table 34. Register 59’h: Global Output Mode ............................................................... 38
Table 35. Register 5A’h: Global Input ISE 1 Long ......................................................... 39
Table 36. Register 5B’h: Global Input ISE 1 Short ........................................................ 39
Table 37. Register 5C’h: Global Input ISE 2 Long ......................................................... 39
Table 38. Register 5D’h: Global Input ISE 2 Short ........................................................ 40
Table 39. Register 5E’h: Global PCIe Control................................................................ 40
Table 40. Register 60’h: Input AEQ Control ................................................................. 40
Table 41. Register 6D’h: Reserved.............................................................................. 41
Table 42. Register 6F’h: Reserved.............................................................................. 41
Table 43. Register 76’h: Rx Detect Delay0................................................................... 41
Table 44. Register 77’h: Rx Detect Delay .................................................................... 42
Table 45. Register 78’h: Serial Address....................................................................... 42
Table 46. Register 7A’h: Reserved.............................................................................. 42
Table 47. Register 7B’h: Reserved.............................................................................. 42
Table 48. Register 7E’h: RevID .................................................................................. 43
Table 49. Register 7F’h: Current Page......................................................................... 43
Table 50. DC Characteristics, High-Speed Data Inputs .................................................. 44
Table 51. DC Characteristics, High-Speed Data Outputs ................................................ 44
Table 52. DC Characteristics, LVTTL I/O Signals ........................................................... 45
Table 53. DC Characteristics, Power Requirements ....................................................... 45
Revision 2.0
September 2010
Confidential
Page 6
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
