VSC6134
Datasheet
Table 429. Global MPU Register 35 - Block Interrupt Mask
Reset
Value
Bit
Name
Access
Description
6
AOTU_FA_INTM
RW
Mask bit for the add path client OTU frame aligner
block.
0
0: Allow add path client OTU frame aligner block to
generate interrupt
1: Mask interrupt
5
4
SYNC_INTM
LOCK_INTM
RW
Mask bit for the sync pulses in Table 406, page 370.
0: Allow sync pulses to generate interrupt
1: Mask interrupt
0
0
R/W
Mask bit for the loss-of-clock and phase-lock
detectors in Table 413, page 375.
0: Allow lock detectors to generate interrupt
1: Mask interrupt
3
DROP_PRBS_INTM
R/W
Mask bit for the drop path line unframed PRBS
monitor.
0
0: Allow drop path line unframed PRBS monitor to
generate interrupt
1: Mask interrupt
2
1
0
DDD_INTM
R/W
R/W
R/W
Mask bit for the DDD circuit.
0: Allow DDD circuit to generate interrupt
1: Mask interrupt
0
0
0
D_RLL_INTM
ADD_PRBS_INTM
Mask bit for the RLL circuit on the drop path.
0: Allow RLL circuit to generate interrupt
1: Mask interrupt
Mask bit for the drop path client unframed PRBS
monitor.
0: Allow drop path client unframed PRBS monitor to
generate interrupt
1: Mask interrupt
388 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
