VSC6134
Datasheet
3.13.28 Global MPU Register 31 - Drop PFD TX Clock Ratio Register
Address:
0x01F
Register Reset Value:
0x00ED
Table 425. Global MPU Register 31 - Drop PFD TX Clock Ratio Register
Reset
Value
Bit
15:10
9:0
Name
Access
RO
Description
Reserved
0x00
DROP_TXCLK_DIV_RATIO[9:0]
R/W
Clock divide value, range is limited to 4-1000. A
transition on the DROP_CLOCK_RATIO_LATCH bit
in Table 421, page 383 is required to activate the
new value in this register.
0x0ED
3.13.29 Global MPU Register 32 - SONET Block Interrupts
Address:
0x020
Register Reset Value:
0x0000
Table 426. Global MPU Register 32 - SONET Block Interrupts
Reset
Value
Bit
Name
Access
Description
15
AS_SOHM_INT
RO
1: Indicates the add path SONET section overhead
monitor block generated an interrupt.
0
0
0
0
0
14
13
12
11
AS_SOHG_INT
AS_LOHM_INT
AS_LOHG_INT
AS_FA_INT
RO
RO
RO
RO
1: Indicates the add path SONET section overhead
generator block generated an interrupt.
1: Indicates the add path SONET line overhead
monitor block generated an interrupt.
1: Indicates the add path SONET line overhead
generator block generated an interrupt.
1: Indicates the add path SONET frame alignment
block generated an interrupt.
10:8
7
Reserved
RO
RO
000
0
DS_SOHM_INT
1: Indicates the drop path SONET section overhead
monitor block generated an interrupt.
6
5
DS_SOHG_INT
DS_LOHM_INT
DS_LOHG_INT
DS_FA_INT
RO
RO
RO
RO
RO
1: Indicates the drop path SONET section overhead
generator block generated an interrupt.
0
0
1: Indicates the drop path SONET line overhead
monitor block generated an interrupt.
4
1: Indicates the drop path SONET line overhead
generator block generated an interrupt.
0
3
1: Indicates the drop path SONET frame alignment
block generated an interrupt.
0
2:0
Reserved
000
385 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
