VSC6134
Datasheet
3.13.25 Global MPU Register 28 - Add PFD RX Clock Ratio Register
Address:
0x01C
Register Reset Value:
0x00ED
Table 422. Global MPU Register 28 - Add PFD RX Clock Ratio Register
Reset
Value
Bit
15:10
9:0
Name
Access
RO
Description
Reserved
0x00
ADD_RXCLK_DIV_RATIO[9:0]
R/W
Clock divide value, range is limited to 4-1000. A
transition on the ADD_CLOCK_RATIO_LATCH bit in
Table 421, page 383 is required to activate the new
value in this register.
0x0ED
3.13.26 Global MPU Register 29 - Add PFD TX Clock Ratio Register
Address:
0x01D
Register Reset Value:
0x00FF
Table 423. Global MPU Register 29 - Add PFD TX Clock Ratio Register
Reset
Value
Bit
15:10
9:0
Name
Access
RO
Description
Reserved
0x00
ADD_TXCLK_DIV_RATIO[9:0]
R/W
Clock divide value, range is limited to 4-1000. A
transition on the ADD_CLOCK_RATIO_LATCH bit in
Table 421, page 383 is required to activate the new
value in this register.
0x0FF
3.13.27 Global MPU Register 30 - Drop PFD RX Clock Ratio Register
Address:
0x01E
Register Reset Value:
0x00FF
Table 424. Global MPU Register 30 - Drop PFD RX Clock Ratio Register
Reset
Value
Bit
15:10
9:0
Name
Access
RO
Description
Reserved
0x00
DROP_RXCLK_DIV_RATIO[9:0]
R/W
Clock divide value, range is limited to 4-1000. A
transition on the DROP_CLOCK_RATIO_LATCH bit
in Table 421, page 383 is required to activate the
new value in this register.
0x0FF
384 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
