VSC6134
Datasheet
Table 435. LVDS Transmit
Symbol
TDTP
Parameter
Minimum
Typical
Maximum
Unit
Clock period
1 / 669.33 MHz
ns
TDTDC
TDTR
Duty cycle
0.4
100
0.5
175
175
0
0.6
250
250
200
20% to 80% rise time
20% to 80% fall time
Clock to Q delay
ps
ps
ps
TDTF
100
TDTCQ
–200
4.2.3
Phase Frequency Discriminator
The following table contains the phase frequency discriminator AC characteristics.
Table 436. Phase Frequency Discriminator Characteristics
Symbol
fVS0
Parameter
Typical
669.33
669.33
19.44
Maximum
693.1
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Clock frequency of VCOSRC0(1)
Clock frequency of VCOSRC1(2)
Clock frequency of RXCLK0DIV
Clock frequency of RXCLK1DIV
Clock frequency of VCO00
Clock frequency of VCO01
Clock frequency of VCO10
Clock frequency of VCO11
fVS1
693.1
fRXD0
fRXD1
fVCO00
fVCO01
fVCO10
fVCO11
19.44
173.37
173.37
173.37
173.37
1. VCOSRC0 is an LVDS input.
2. VCOSRC1 is an LVDS input.
392 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
