VSC6134
Datasheet
3.13.12 Global MPU Register 11 - Scratch
Address:
0x00B
Register Reset Value:
0x0000
Table 409. Global MPU Register 11 - Scratch
Reset
Value
Bit
Name
Access
Description
15:0
SCRATCH[15:0]
R/W
Scratch register used for writing and reading to the
device without affecting device operation.
0x0000
3.13.13 Global MPU Register 12 - Interface Control
Address:
0x00C
Register Reset Value:
0x0000
Table 410. Global MPU Register 12 - Interface Control
Reset
Value
Bit
15
14
Name
Access
RO
Description
Reserved
0
0
AUTO_DTK_GEN
R/W
When set to 1, this bit enables the generation of an
automatic internal data acknowledge signal sixteen
microprocessor clock (mpu_clk) clock cycles after
the beginning of a bus cycle.
13
DTK_TRI_PRG
R/W
This bit affects the time at which the DTKN signal is
tristated in the synchronous modes.
0
0: Causes the DTKN signal to be tristated one half
clock cycle after the bus cycle has ended.
1: Causes the DTKN signal to be tristated when chip
select is de-asserted.
12:11
10
Reserved
RO
00
0
ADD_TOHI_CLK_INV
R/W
This bit selects the clock edge that the serial SONET
transport overhead data is sampled on.
0: Data sampled on rising edge of clock
1: Data sampled on falling edge of clock
9
DROP_TOHI_CLK_INV
Reserved
R/W
RO
This bit selects the clock edge that the serial SONET
transport overhead data is sampled on.
0: Data sampled on rising edge of clock
1: Data sampled on falling edge of clock
0
8:0
0x00
372 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
