VSC6134
Datasheet
3.12.2
Drop PRBS Generator Configuration Register
Address:
0x304
Register Reset Value:
0x0000
Table 389. Drop PRBS Generator Configuration Register
Reset
Value
Bit
Name
Access
Description
15
PRBSGEN_ENA
R/W
Enable PRBS generator on the client side interface.
0
1: Enable
0: Disable
14:13
PRBSGEN_SEL[1:0]
PRBSGEN_INV
R/W
R/W
Select sequence length.
00: 215 – 1
00
01: 220 – 1
10: 223 – 1
11: 231 – 1
12
Invert output sequence.
1: No invert
0
0: Invert
11
PRBSGEN_INSERR
Reserved
R/W
RO
Every 0 to 1 transition of this bit inserts an error in the
generated pseudoramdom data.
0
10:0
0x000
3.12.3
Add PRBS Checker Configuration Register
Address:
0x904
Register Reset Value:
0x0000
Table 390. Add PRBS Checker Configuration Register
Reset
Value
Bit
Name
Access
Description
15
PRBSCHK_ENA
R/W
Enable PRBS checker on the client side interface.
0
1: Enable
0: Disable
14:13
PRBSCHK_SEL[1:0]
R/W
Select sequence length.
00: 215 – 1
00
01: 220 – 1
10: 223 – 1
11: 231 – 1
12
PRBSCHK_INV
Reserved
R/W
RO
Compare input data with inverted sequence.
1: No invert
0: Invert
0
11:0
0x000
360 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
