VSC6134
Datasheet
3.12
Programmable PRBS Generator and Checker Registers
The programmable PRBS generator and checker registers and configuration bits are shown in the
following sections.
3.12.1
Add PRBS Generator Configuration Register
Address:
0x900
Register Reset Value:
0x0000
Table 388. Add PRBS Generator Configuration Register
Reset
Value
Bit
Name
Access
Description
15
PRBSGEN_ENA
R/W
Enable PRBS generator on the line side interface.
0
1: Enable
0: Disable
14:13
PRBSGEN_SEL[1:0]
PRBSGEN_INV
R/W
R/W
Select sequence length.
00: 215 – 1
00
01: 220 – 1
10: 223 – 1
11: 231 – 1
12
Invert output sequence.
1: No invert
0
0: Invert
11
PRBSGEN_INSERR
Reserved
R/W
RO
Every 0 to 1 transition of this bit inserts an error in the
generated pseudo-ramdom data.
0
10:0
0x000
359 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
