VSC6134
Datasheet
3.2.5
LOHM BIP-8 Bit Error Counter (MSW) Register
Address:
0xDF0: Add Path
0x5F0: Drop Path
0x0000
Register Reset Value:
Table 101. LOHM Bit Error Counter (MSW) Register
Reset
Value
Bit
15:8
7:0
Name
Access
RO
Description
Reserved
0x00
0x00
B2BITERRCNT[23:16]
RO
Upper portion of the B2 BIP error counter
3.2.6
LOHM BIP-8 Error Counter (LSW) Register
Address:
0xDF1: Add Path
0x5F1: Drop Path
0x0000
Register Reset Value:
Table 102. LOHM Bit Error Counter (LSW) Register
Reset
Value
Bit
Name
Access
Description
15:0
B2BITERRCNT[15:0]
RO
Lower portion of B2 BIP-8 error count. Depending on
configuration signal B2BITCNT_SEL, bit or block errors will
be counted within one second period. To access 24-bit
counter two consecutive read cycles required. The first
cycle accesses the most significant word [23:16]; the
second cycle accesses the least significant word [15:0]
0x0000
3.2.7
LOHM BIP-8 Block Error Counter (MSW) Register
Address:
0xDF2: Add Path
0x5F2: Drop Path
0x0000
Register Reset Value:
Table 103. LOHM BIP-8 Block Error Counter (MSW) Register
Reset
Value
Bit
15:5
4:0
Name
Access
RO
Description
Reserved
0x00
0x00
B2BLKERRCNT[20:16]
RO
Upper portion of the B2 Block Error counter [20:16]
230 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
