VSC6134
Datasheet
3.3
Section Overhead Monitor Registers
The section overhead (SOH) monitor registers and configuration bits are shown in following sections.
3.3.1
SOH Monitor Z0 Byte Registers
Address:
0xC00 to 0xC5F: Add Path
0x400 to 0x45F: Drop Path
0x0000
Register Reset Value:
Table 110. SOH Monitor Z0 Byte Registers
Reset
Value
Bit
Name
Access
Description
15:0
Z0BYTE
RO
Z0 bytes beginning with one byte of J0. J0 is located at bits
[15:8] of register address 0xC00 (add) and 0x400 (drop),
while the first Z0 byte is located at bits [7:0] of address
0xC00 (add) and 0x400 (drop).
0x0000
3.3.2
BER Monitor Configuration Register
Address:
0xC60: Add Path
0x460: Drop Path
0x0000
Register Reset Value:
Table 111. BER Monitor Configuration Register
Reset
Value
Bit
Name
Access
Description
15
CNT_CLR_CTRL
R/W
Selects between the leaky bucket algorithm and rate
detection.
0
1: Rate detection, where SDERR_CNT and SFERR_CNT
are cleared at the end of the monitored block. Decrement
and clear thresholds are ignored in this mode.
0: Leaky bucket algorithm (default);
14
B2B1N_SEL
Reserved
R/W
RO
Selects the source of BIP errors:
1: Counts B2 errors from B2 monitor;
0: Counts B1 errors from B1 monitor (default)
0
13:0
0x000
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
