VSC6134
Datasheet
3.2.4
LOHM Interrupt Status Register
Address:
0xDEF: Add Path
0x5EF: Drop Path
0x0000
Register Reset Value:
Table 100. LOHM Interrupt Status Register
Reset
Value
Bit
15
14
13
12
11
10
9
Name
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
B2ERR_S
K1K2NEW_S
K1INC_S
AIS_S
B2 BIP-8 error interrupt status bit.
0
0
0
0
0
0
0
0
New K1 and K2 byte change of state interrupt bit (delta).
APS inconsistent K1 change of state bit (delta).
AIS_L change of state interrupt bit (delta).
RDI_L change of state interrupt bit (delta).
APS mode mismatch change of state interrupt bit (delta).
New S1 byte synchronization change of state bit (delta).
RDI_S
APSMM_S
S1NEW_S
S1INC_S
8
S1 byte inconsistent message change of state interrupt bit
(delta).
7
6
M0M1ERR_S
LDCC_S
R/W
R/W
M0 and M1 byte REI_L interrupt status bit.
0
0
Line DCC interrupt status bit. The status is set when full
Line DCC message extracted from consecutive 24 frames
(once every 24 frames).
5
E2NEW_S
R/W
E2 byte interrupt status bit. The status is set when the new
E2 byte is received.
0
4
3
2
1
0
K1INC_L
AIS_L
R/W
R/W
R/W
R/W
R/W
Inconsistent K1 state bit (live).
AIS_L state bit (live).
0
0
0
0
0
RDI_L
RDI_L state bit (live).
APSMM_L
S1INC_L
APS mode mismatch state bit (live).
S1 byte inconsistent message state bit (live).
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
