VSC6134
Datasheet
Table 99. LOHM Interrupt Mask Register (continued)
Reset
Value
Bit
Name
Access
Description
9
S1NEW_M
R/W
Mask for S1 alarm interrupt status bit
1: Mask interrupt
1
0: Allow S1_S generate the interrupt
8
7
S1INC_M
R/W
R/W
R/W
R/W
RO
Mask for inconsistent S1 message interrupt status bit
1: Mask interrupt
0: Allow S1INC_S generate the interrupt
1
M0M1ERR_M
LDCC_M
Mask for REI_L interrupt status bit
1: Mask interrupt
0: Allow M0M1ERR_S generate the interrupt
1
6
Mask for LDCC_S interrupt status bit
1: Mask interrupt
0: Allow LDCC_S generate the interrupt
1
5
E2NEW_M
Reserved
Mask for E2NEW_S interrupt status bit
1: Mask interrupt
0: Allow E2NEW_S generate the interrupt
1
4:0
0x00
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
