VSC6134
Datasheet
3.2
Line Overhead Monitor Registers
The line overhead monitor (LOHM) registers and configuration bits are described in the following
tables.
3.2.1
LOHM Line DCC Message Registers
Address:
0xD80 to 0xDEB (108 addresses): Add Path
0x580 to 0x5EB (108 addresses): Drop Path
0x0000
Register Reset Value:
Table 97. LOHM Line DCC Message Registers
Reset
Value
Bit
Name
Access
Description
15:0
LDCCBYTEn[15:0]
RO
Line DCC bytes accumulated for 24 consecutive
frames.The bytes are stored in the memory in the order
they are received, that is,
0x0000
LDCCBYTE0[15:8] - D4, LDCCBYTE0[7:0] - D5,
LDCCBYTE1[15:8] - D6, LDCCBYTE1[7:0] - D7,
LDCCBYTE2[15:8] - D8, LDCCBYTE2[7:0] - D9,
LDCCBYTE3[15:8] - D10, LDCCBYTE3[7:0] - D11,
LDCCBYTE4[15:8] - D12, LDCCBYTE4[7:0] - D4,
LDCCBYTE5[15:8] - D5, LDCCBYTE5[7:0] - D6,
.
.
.
LDCCBYTEn[15:8] - D11, LDCCBYTEn[7:0] - D12,
and so forth, where n = (0 to 107)
3.2.2
LOHM Configuration Register
Address:
0xDEC: Add Path
0x5EC: Drop Path
0x0000
Register Reset Value:
Table 98. LOHM Configuration Register
Reset
Value
Bit
Name
Access
Description
15
K1K2FRM
R/W
Defines the number of consecutive frames for AIS_L,
RDI_L and APS mode mismatch detection.
1: For SDH applications - 3 frames.
0
0: For SONET applications - 5 frames (default).
14
APSARC
R/W
Defines the valid APS architecture for the current
equipment (bit 3 in K2 byte).
0
1: If provisioned for 1:n mode.
0: If provisioned for 1+1 mode (default).
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
