VSC6134
Datasheet
Table 95. Add DW Overhead Processor/FEC Performance Monitor Registers (continued)
Address
0xF10
0xF11
0xF12
0xF13
0xF14
0xF15
0xF16
0xF17
0xF18
0xF19
0xF1A
0xF1B
0xF1C
0xF1D
0xF20
0xF21
0xF22
0xF23
0xF24
0xF26
0xF27
0xF28
0xF29
0xF2A
Register Name
Reference
Standard FEC Uncorrectable Code Word Count (LSW)
Standard FEC Uncorrectable Code Word Count (MSW)
Standard FEC Opposite Surround Bit Error Count (LSW)
Standard FEC Opposite Surround Bit Error Count (MSW)
Standard FEC Same Surrounds Bit Error Count (LSW)
Standard FEC Same Surrounds Bit Error Count (MSW)
Standard FEC Corrected Bit Error Count (LSW)
Standard FEC Corrected Bit Error Count (MSW)
Standard FEC Early Transition Bit Error Count (LSW)
StandardFEC Early Transition Bit Error Count (MSW)
Standard FEC Late Transition Bit Error Count (LSW)
Standard FEC Late Transition Bit Error Count (MSW)
Standard FEC Corrected Symbol Error Count (LSW)
Standard FEC Corrected Symbol Error Count (MSW)
DW Overhead Monitor APS/PCC MSW Register
DW Overhead Monitor APS/PCC LSW Register
DW Overhead Monitor FTFL Configuration Register
DW Overhead Monitor FTFL FIFO Access Register
DW Overhead Monitor GCC Configuration Register 1
DW Overhead Monitor GCC FIFO Access Register
DW Overhead Monitor Configuration Register
See Section 3.8.19, page 295.
See Section 3.8.20, page 295.
See Section 3.8.21, page 295.
See Section 3.8.22, page 296.
See Section 3.8.23, page 296.
See Section 3.8.24, page 296.
See Section 3.8.25, page 297.
See Section 3.8.26, page 297.
See Section 3.8.27, page 297.
See Section 3.8.28, page 298.
See Section 3.8.29, page 298.
See Section 3.8.30, page 298.
See Section 3.8.31, page 299.
See Section 3.8.32, page 299.
See Section 3.8.33, page 299.
See Section 3.8.34, page 299.
See Section 3.8.35, page 300.
See Section 3.8.36, page 301.
See Section 3.8.37, page 302.
See Section 3.8.38, page 302.
See Section 3.8.39, page 303.
See Section 3.8.40, page 304.
See Section 3.8.41, page 304.
See Section 3.8.42, page 305.
DW Overhead Monitor Section Monitor TTI FIFO Register
DW Overhead Monitor Section Monitor Configuration Register
DW Overhead Monitor Section Monitor BIP-8 Bit Error Count
Register (MSW)
0xF2B
0xF2C
0xF2D
0xF2E
0xF2F
DW Overhead Monitor Section Monitor BIP-8 Bit Error Count
Register (LSW)
See Section 3.8.43, page 305.
See Section 3.8.44, page 305.
See Section 3.8.45, page 306.
See Section 3.8.46, page 306.
See Section 3.8.47, page 306.
DW Overhead Monitor Section Monitor BIP-8 Block Error
Count Register (MSW)
DW Overhead Monitor Section Monitor BIP-8 Block Error
Count Register (LSW)
DW Overhead Monitor Section Monitor BEI Count Register
(MSW)
DW Overhead Monitor Section Monitor BEI Count Register
(LSW)
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
