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Datasheet
Figure 17. Layout of the GCC FIFO Buffer
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2 GCCs
3 GCCs
2.7.5.11
Experimental Overhead (EXP)
The operation of the EXP byte generator is controlled by ADD/DROP_TP_RES. Decoding for
ADD/DROP_TP_RES is shown in the following table.
Table 29. EXP Generator Control
ADD_TP_RES
Function
0
1
The EXP bytes are sourced from the FPGA1
The EXP bytes are sourced from the received data in the OTUk to FEC or FEC loopback
modes respectively.
1. In the non-FPGA mode, zeros are inserted for the reserved bytes
2.7.5.12
Reserved Overhead (RES)
The operation of the ODU RES byte generator is controlled by ADD/DROP_TP_RES. Decoding for
ADD/DROP_TP_RES is shown in the following table.
Table 30. ODU RES Generator Control
ADD_TP_RES
Function
0
1
The ODU RES bytes are sourced from the FPGA1
The ODU RES bytes are sourced from the received data in the OTUk to FEC or FEC
loopback modes respectively.
1. In the non-FPGA mode, zeros are inserted for the reserved bytes.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
