VSC6134
Datasheet
2.7.5.10
GCCx Generation
When ADD/DROP_TP_GCC = 0 the GCC bytes are generated according to ADD_GCCG_CFG[2:0].
Decoding ADD_GCCG_CFG[2:0] is shown in the following table. When ADD/DROP_TP_GCC = 1,
the GCC bytes are sourced from the received DWOH data. See Figure 17, page 95 for the layout of the
GCC data within the buffer.
Table 28. GCCx Interface Configuration
Enable Status1,2,3
ADD_GCCG_CFG[2:0]
GCC0
GCC1
GCC2
000
001
010
011
100
101
110
F
T
F
T
F
M
T
T
M
M
T
T
M
T
M
M
M
M
T
M
T
M
M
111
M
1. F = Sourced from FPGA.
2. M = Sourced from a microprocessor using a FIFO.
3. T = Transparent (sourced from received DWOH data). In the SONET mode these bytes are set to zeros.
The FIFO for inserting GCC through the microprocessor interface is designed as a 256 × 6 bit
ping-pong buffer. An interrupt bit ADD_GCCG_RDY (with corresponding mask bit
ADD_GCCG_RDYM) is used to indicate to the microprocessor when one bank of the ping-pong buffer
was read and the device is ready to receive the next set of data. The GCC FIFO is accessible through a
single microprocessor address. A pointer ADD/DROP_GCCG_MPNT[7:0] points to the
ADD/DROP_GCCG[15:0] location that is written from the microprocessor in the
ADD/DROP_GCCG[255:0][15:0] stack. ADD/DROP_GCCG_MPNTI[1:0] is used to set the automatic
increment value of ADD/DROP_GCCG_MPNT[7:0]. The possible values are 1, 2, and 3 encoded by
01, 10, and 11 respectively.
A pointer ADD/DROP_GCCG_SPNT[7:0] points to the ADD/DROP_GCCG[15:0] location that is read
by the system from the ADD/DROP_GCCG[255:0][15:0] stack.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
