VSC6134
Datasheet
ADD/DROP_PM_TTI_PNT[5:0] can be written to or read by the microprocessor.
ADD/DROP_PM_TTI_PNT[5:0] is incremented automatically after each access to
ADD/DROP_PM_TTI[15:0].
2.7.5.8
Automatic Protection Switching and Protection Control Channel
The operation of the APS/PCC byte generator is controlled by ADD/DROP_APSCTRL[1:0]. Decoding
for ADD/DROP_APSCTRL[1:0] is shown in the following table.
Table 26. ADD/DROP_APSCTRL Decoding
ADD_APSCTRL[1:0]
Function
00
The APS/PCC bytes are sourced from microprocessor accessible registers
ADD/DROP_APS_GEN[3:0][7:0].
01
10
The APS/PCC bytes are sourced from the FPGA1.
The APS/PCC bytes are sourced from the received data in the OTUk to FEC or
FEC loopback modes.
11
Reserved
1. In the non-FPGA mode, zeros are inserted for the reserved bytes.
2.7.5.9
Fault Type and Fault Location Reporting Channel (FTFL)
The operation of the FTFL byte generator is controlled by ADD/DROP_FTFLCTRL[1:0]. Decoding for
ADD/DROP_FTFLCTRL[1:0] is shown in the following table.
Table 27. ADD/DROP_FTFLCTRL Decoding
ADD_FTFLCTRL[1:0]
Function
00
The FTFL byte is sourced from the microprocessor programmable registers
ADD/DROP_FTFL_GEN[127:0][15:0]
01
10
The FTFL byte is sourced from the FPGA1.
The FTFL byte is sourced from the received data in the OTUk to FEC or FEC
loopback modes.
11
Reserved
1. In the non-FPGA mode, zeros are inserted for the reserved bytes.
ADD/DROP_FTFL_GEN[127:0][15:0] is implemented as a stack and is accessible through a single
microprocessor address. The ADD/DROP_FTFL_GEN_PNT[6:0] pointer points to the
ADD/DROP_FTFL_GEN[15:0] location which is written to or read from the stack by the next
microprocessor write/read to ADD/DROP_FTFL_GEN[15:0].
ADD/DROP_FTFL_GEN_PNT[6:0] can be written to or read by the microprocessor.
ADD/DROP_FTFL_GEN_PNT[6:0] is incremented automatically after each access to
ADD/DROP_FTFL_GEN[15:0].
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
