VSC6134
Datasheet
2.7.5.14
OPUk Reserved Overhead (RES)
The operation of the OPU RES byte is controlled by ADD_TP_RES. Decoding for ADD_TP_RES
generator is shown in the following table.
Table 32. OPU RES Generator Control
ADD_TP_RES
Function
0
1
The OPU RES bytes are sourced from the FPGA1
The OPU RES bytes are sourced from the received data in the OTUk to FEC or FEC
loopback modes respectively.
1. In the non-FPGA mode, zeros are inserted for the reserved bytes.
2.7.5.15
OPUk Justification Bytes
The operation of the OPU Justification byte generator is controlled by ADD/DROP_TP_JB. Decoding
for ADD/DROP_TP_JB is shown in the following table.
Table 33. ADD/DROP_TP_JB
ADD/DROP_TP_JB
Function
0
1
The OPU Justification bytes are sourced from the FPGA1
The OPU Justification bytes are sourced from the received data in the OTUk to FEC or
FEC loopback modes respectively.
1. In the non-FPGA mode, zeros are inserted for the reserved bytes.
Note that when the asynchronous mapping mode is used, ADD/DROP_TP_JB must be set to 1.
2.7.5.16
ODUk AIS Generation
ODUk-AIS can be generated:
●
●
●
Automatically when the add/drop OTUk frame aligner goes into a loss of frame (LOF) state. This is
activated by setting ADD/DROP_LOF_AIS to 1.
Automatically when the drop FEC frame aligner detects loss of frame (LOF). This is activated by
setting ADD_LOFD_AIS to 1.
Manually by setting a microprocessor accessible bit. ODUk-AIS is continuously generated when
ADD/DROP_ODU_AIS_EN is set to 1.
2.7.5.17
ODUk OCI Generation
ODUk-OCI can be generated:
●
●
●
Automatically when the add OTUk frame aligner goes into a loss of signal (LOS) state. This is
activated by setting ADD_LOS_OCI to 1.
Automatically when the drop FEC frame aligner detects loss of signal (LOS). This is activated by
setting ADD_LOSD_AIS to 1.
Manually by setting a microprocessor accessible bit. ODUk-OCI is continuously generated when
ADD/DROP_ODU_OCI_EN is set to 1.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
