VSC6134
Datasheet
2.7.5.7
Path Monitor (PM) Overhead Generation
The content of the PM fields is a pattern of repeating all-ones, 0110 0110, or 0101 0101 during the
presence of a corresponding maintenance signal such as ODUk-AIS, ODUk-OCI or ODUk-LCK. In the
absence of a maintenance signal, the generation of the PM field is controlled by a microprocessor
programmable register. When TCMi updating is disabled, the bytes are:
●
●
●
Sourced from FPGA
Set to 0x00 in non-FPGA mode
Passed transparently in OTUk to FEC or FEC Loopback modes
The only exception to all of the above conditions is the OTUk-AIS signal when all transmitted bytes are
overwritten with a PN-11 sequence.
The update of the ODUk PM subfields is controlled (enabled or disabled) using microprocessor
programmable bits ADD/DROP_PMCTRL[1:0]. The decoding for ADD/DROP_PMCTRL[1:0] is
shown in the following table.
Table 25. ADD/DROP_PMCTRL[1:0] Decoding
ADD/DROP_PMCTRL[1:0]
Function
00
PM TTI bytes are sourced from a 32 × 16-bit array,
ADD/DROP_PM_TTI[31:0][15:0], and inserted in 64 consecutive frames, aligned
with the MFAS.
PM BIP-8 is computed over the bits in the OPUk columns of OTUk frame i and is
inserted OTUk frame i + 2.
PM BDI bit is set when there is a drop signal fail condition on the drop path. Drop
signal fail (DSF) is declared when either an LOS or LOF or both are detected. SF is
programmed by the OTU_BDISF[1:0] bits.
PM BEI count is sourced from the OTUk overhead monitor block.
PM STAT is sourced from the microprocessor accessible register PM_STAT[2:0].
This register has a default value of 001.
01
All PM subfields, except for PM BIP-8, are sourced from the FPGA1.
PM BIP-8 is computed over the bits in the OPUk of OTUk frame i and is inserted in
OTUk frame i + 2.
10
11
All PM subfields are sourced from the received data.
PM TTI bytes are sourced from a 32 × 16-bit array,
ADD/DROP_PM_TTI[31:0][15:0], and inserted in 64 consecutive frames, aligned
with the MFAS.
PM BIP-8 is computed over the bits in the OPUk columns of OTUk frame i and is
inserted in OTUk frame i + 2.
PM BDI bit is sourced from the FPGA
PM BEI count is sourced from the FPGA.
PM STAT is sourced from the microprocessor accessible register PM_STAT[2:0].
This register has a default value of ‘001.
1. In the non-FPGA mode, zeros are inserted for the reserved bytes.
ADD/DROP_PM_TTI[31:0][15:0] is implemented as a stack and is accessible through a single
microprocessor address.The ADD/DROP_PM_TTI_PNT[5:0] pointer points to the
ADD/DROP_PM_TTI[15:0] location that is written to or read from the stack by the next
microprocessor write/read to ADD/DROP_PM_TTI[15:0].
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
