VSC6134
Datasheet
2.7.5.4
OTUk Section Monitor (SM)
Update of the OTUk SM subfields is controlled (enabled or disabled) using microprocessor
programmable bits ADD/DROP_SMCTRL[1:0]. Decoding for ADD/DROP_SMCTRL[1:0] is shown in
the following table.
Table 22. ADD/DROP_SMCTRL[1:0] Decoding
ADD/DROP_SMCTRL[1:0]
Function
00
SM TTI bytes are sourced from a 32 × 16-bit array, SM_TTI[31:0][15:0], and
inserted in 64 consecutive frames, aligned with the MFAS.
SM BIP-8 is computed over the bits in the OPUk columns of OTUk frame i and is
inserted in OTUk frame i+2.
SM BDI bit is set on the add side when there is a drop signal fail condition on the
drop path and is set on the drop side when there is an add signal fail condition on
the add path. Drop signal fail (DSF) or add signal fail (ASF) are declared when
either an LOS or LOF or both are detected. SF is programmed by the
OTU_BDISF[1:0] bits.
SM BEI count is sourced from the OTUk overhead monitor block.
SM IAE is set on the add side to indicate when the add OTUk frame aligner (OTUk
to FEC mode) or the drop FEC frame aligner (FEC regenerator mode) has entered
the OOF state when add AUTO_SMIAE = 1. On the drop side it is set to indicate
the drop FEC frame aligner has entered the OOF state when drop
AUTO_SMIAE = 1. IAE is asserted for 16 multiframes on each assertion of
FEC_OOF. Each new declaration of IAE restarts the 16 multiframe insertion
counter. IAE can be declared at any time through the microprocessor by a 0 to 1
transition on microprocessor programmable bit SM_IAE. Each 0 to1 transition
causes IAE to be asserted for 16 multiframes.
SM Reserved bits are sourced from received data in the OTUk to FEC or FEC
loopback modes, or are sourced from the FPGA1 in SONET/Transparent mode.
01
All SM subfields, except for SM BIP-8, are sourced from the FPGA1.
SM BIP-8 is computed over the bits in the OPUk of OTUk frame i and is inserted in
OTUk frame i + 2.
10
11
All SM subfields are sourced from the received DWOH data.
SM TTI bytes are sourced from a 32 × 16-bit array, SM_TTI[31:0][15:0], and
inserted in 64 consecutive frames, aligned with the MFAS.
SM BIP-8 is computed over the bits in the OPUk columns of OTUk frame i and is
inserted in OTUk frame i + 2.
SM BDI bit is sourced from the FPGA
SM BEI count is sourced from the FPGA.
SM IAE is set on the add side to indicate when the add OTUk frame aligner (OTUk
to FEC mode) or the drop FEC frame aligner (FEC regenerator mode) has entered
the OOF state when add AUTO_SMIAE = 1. On the drop side it is set to indicate
the drop FEC frame aligner has entered the OOF state when drop
AUTO_SMIAE = 1. IAE is asserted for 16 multiframes on each assertion of
FEC_OOF. Each new declaration of IAE restarts the 16 multiframe insertion
counter. IAE can be declared at any time through the microprocessor by a 0 to 1
transition on microprocessor programmable bit SM_IAE. Each 0 to1 transition
causes IAE to be asserted for 16 multiframes.
SM Reserved bits are sourced from received data in the OTUk to FEC or FEC
Loopback modes or are sourced from the FPGA1 in SONET/Transparent mode.
1. In the non-FPGA mode, zeros are inserted for the reserved bytes.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
