VSC6134
Datasheet
TXOCHD0 and TXOCHD1 are each written into a 16 word × 64 bit storage. The storage is read using
the 167 MHz clock. If writes do not take place (that is, either TXOCHFS0 or TXOCHFS1 is missing),
the location pointers do not change and old data is read from the last read location until the frame sync
comes back.
2.7.5.2
FAS Generator
The operation of the FAS generator is controlled by ADD/DROP_FASCTRL[1:0]. Decoding for
ADD/DROP_FASCTRL[1:0] is shown in the following table.
Table 20. ADD/DROP_FASCTRL Decoding
ADD/DROP_FASCTRL[1:0]
Function
00
The FAS bytes are sourced from the microprocessor programmable registers
FAS_REG[2:0][15:0].
01
10
The FAS bytes are sourced from the FPGA.
The FAS bytes are sourced from the received OTUk data.
2.7.5.3
MFAS Generator
The function of the MFAS generator is described in the following table.
Table 21. MFASCTRL Decoding
MFASCTRL
Function
0
The MFAS byte is either sourced from the received OTUk data streams in the OTUk to FEC
or FEC Loopback modes, or is generated on the device in the SONET/Transparent mode.
1
The MFAS byte is sourced from the FPGA(1)
.
1. In the non-FPGA mode, zeros are inserted for the reserved bytes.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
