VSC6134
Datasheet
2.7.3
2.7.4
Asynchronous Mapping
The add path clock crossing FIFO is capable of mapping an asynchronous CBR10G payload (for
example, SONET/SDH) into the FEC frame. The ADD_ASYNC bit enables the asynchronous mapping
mode of the add path. In this mode, the clock crossing buffer justifies the incoming data as it is mapped
into the FEC frame. A sample of the read and write pointers is taken at an interval of a FEC frame row.
Justifications occur when the read pointer is outside the two internally set, upper and lower thresholds.
BIP-8 Calculation
BIP-8 is computed over the bits in the OPUk columns of OTUk frame i and is inserted in the OTUk
frame i + 2. The BIP8 block I/O is shown in the following table. BIP-8 cannot be inserted from the serial
FPGA interface.
Table 18. BIP8 Block I/O Description
Name
Direction
Function
tx_resetn
tx_clk
IN
IN
IN
IN
IN
IN
Transmit reset.
Transmit clock.
sfsync
Single frame sync marks the OTUk overhead in each row.
Column count tracks the words in each row of the data input.
Multi-frame sync marks the start of the OTUk frame.
col_cnt[8:0]
multifs
encdatain[63:0]
Encoder data in is the OTUk frame with all the overhead and payload but
with placeholders for the parity bytes.
smbip8[7:0]
bip8[7:0]
OUT
OUT
SM BIP8 needs special timing to be inserted correctly into the OTUk frame
so it comes out one clock early.
BIP8.
2.7.5
Digital Wrapper Overhead (DWOH) Generator
The digital wrapper overhead generator exists in two places in the VSC6134 and optionally inserts
digital wrapper overhead bytes into the outgoing OTUk or EFEC frames on the line (add) side and into
the outgoing OTUk frames on the client (drop) side. The data to be inserted can be sourced from a serial
interface or from on-chip storage. Note that reserved or undefined fields of the digital wrapper overhead
cannot be sourced from on-chip storage and must be sourced from the serial interface if nonzero values
are to be inserted for these bytes. The following sections describe many microprocessor control signals
of which there is a corresponding set for both the add-side and drop-side DWOH generators.
2.7.5.1
Digital Wrapper Overhead-Generator Serial Interface
Serial data can be delivered to the VSC6134 for insertion into the digital wrapper overhead fields of the
OTUk or EFEC frames. The following signals are used to interface with an external device such as an
FPGA:
LINE (ADD) side:
●
●
ADDOHCLK0
TXOCHFS0
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
