VSC6134
Datasheet
Table 17. Clock Crossing Block I/O Description
Name
Direction
Function
Transmit Clock Domain
tx_clk
IN
IN
Transmit clock.
tx_resetn
Transmit clock domain reset.
Add clock enable.
add_clken
mp_stfch_en
mg_fifopr
IN
IN
Stuff enable controls insertion of data into the OTUk stuff bytes.
FIFO pointer reset forced due to FIFO spill.
Stuff data.
IN
stuff_data
mg_newnfa
rll_lock
IN
IN
New frame alignment.
RLL lock.
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
pm_spill
FIFO spill detected.
global_mode_167
data_out
Synchronized global mode bits.
Data out.
nfa_out
OTUk new frame alignment out.
OTUk frame start out.
OTUk overhead sync out.
Column count out.
otu_fstart_out
otu_ov_out
ccount_out
rcount_out
Row count out.
2.7.2
FIFO Spill Detection
The clock crossing FIFO has a spill detector circuit that monitors its read and write pointers for
overflow and underflow conditions. A spill detection may also cause an new frame alignment in the
upstream frame aligner (on the device) to occur, dependent on how the three configuration registers in
the Add Decoder Configuration registers are programmed. The indication of a spill is reported in the
Add Decoder Status register. DROP_FIFO_SPILL and its interrupt can be masked with
DROP_FIFO_SPILLM.
If an NFA or pointer reset is to be asserted automatically upon spill detection, AUTO_NFA_FIFOSPILL
should be set high. To choose whether NFA or a FIFO pointer reset should be asserted, use NFA_FPRN
as follows: If AUTO_NFA_FIFOSPILL is high and NFA_FPRN is high, then an NFA is forced when a
spill detection occurs. When AUTO_NFA_FIFOSPILL is high and NFA_FPRN is low, then a FIFO
pointer reset is asserted when a spill detection occurs. If AUTO_NFA_FIFOSPILL is low, neither an
NFA or FIFO pointer reset is asserted when a spill is detected. One other configuration register
FIFOSPILL_NFAONLOCK is used to determine whether the device must be in PLL/RLL lock before a
spill detection forces NFA or a FIFO pointer reset to be asserted. If it is high when
AUTO_NFA_FIFOSPILL is high, an NFA or FIFO pointer reset is only asserted on spill detection if the
device is in PLL lock for synchronous mapping or RLL lock for asynchronous mapping. If
FIFOSPILL_NFAONLOCK is low, then NFA or FIFO pointer reset is asserted any time
AUTO_NFA_FIFOSPILL is high and a spill is detected.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
