VSC6134
Datasheet
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TXOCHD0
CLIENT (DROP) side:
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DROPOHCLK1
TXOCHFS1
TXOCHD1
The transmit FEC 167-MHz clocks are divided by 3 to generate the transmit digital wrapper overhead
clocks, ADDOHCLK0 and DROPOHCLK1, which run at a frequency of 55.77 MHz. These output
clocks are used by the external device to generate the transmit overhead frame synchronization pulses
(TXOCHFS0 and TXOCHFS1) and transmit digital wrapper overhead information (TXOCHD0 and
TXOCHD1) for insertion into the FEC frames. The transmit digital wrapper overhead serial interface
timing is shown in the following figure.
Figure 16. Transmit Digital Wrapper Overhead Serial Interface Timing
Internal 167
MHZ TX CLK
ADDOHCLK0/
DROPOHCLK1
ts (setup time)
TXOCHFS0/
TXOCHFS1
(Frame sync)
TXOCHD0/
TXOCHD1
(MSB of FAS overhead byte #1)
Cycle #1
Cycle #2
Cycle #680
There are 680 ADDOHCLK0 cycles between the TXOCHFS0 frame syncs, as well as between
DROPOHCLK1 and TXOCHFS1. The following table summarizes the location of the overhead
information between two consecutive frame syncs.
Table 19. TXOCHD Input Overhead Content
Cycle Number
Description
1-128
16 bytes of the overhead for the first row of the OTUk frame.
Idle bits ignored by the device (can be all ones or all zeros).
16 bytes of the overhead for the second row of the OTUk frame.
Idle bits ignored by the device (can be all ones or all zeros).
16 bytes of the overhead for the third row of the OTUk frame.
Idle bits ignored by the device (can be all ones or all zeros).
16 bytes of the overhead for the fourth row of the OTUk frame.
Idle bits ignored by the device (can be all ones or all zeros).
129-170
171-298
299-340
341-468
469-510
511-638
639-680
86 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
