VSC6134
Datasheet
2.4
Line Overhead Generator
The following functions are supported by the line overhead generator (LOH) block:
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AIS-P insertion
Line (B2) BIP-8 generation, insertion, and corruption
K1, K2[7:3], and K2[2:0] (RDI-L) insertions
S1, E2, and reserve bytes insertions
M1/M0 and M1 insertions (REI-L)
Line bypass mode
The LOH generator I/O description is shown in the following table.
Table 7.
LOH Generator I/O Signals
Name
Direction
Function
Receive Direction
TX_CLK
IN
IN
155 MHz system transmit clock.
TX_RESET_N
Active low reset synchronous to the transmit input clock
(TX_CLK).
RX_CLK
IN
IN
155 MHz system receive clock.
RX_RESET_N
Active low reset synchronous to the receive input clock
(RX_CLK).
SDH_SL_MODE
DATAI[BW-1:0]
IN
IN
Global Line And Section Terminator mode selection.
155 Mbps input data bus. DATAI is clocked in on the rising
edge of CLK. Bit BW-1 is the MSB.
NFA
IN
IN
New frame alignment indication.
Row count input.
ROWCNTI[3:0]
COLCNTI[5:0]
SETCNTI[4:0]
DATAO[BW-1:0]
IN
Column count input.
Set count input.
IN
OUT
155 Mbps data bus output. DATAO is clocked out on the rising
edge of CLK. Bit BW-1 is the MSB.
ROWCNTO[3:0]
COLCNTO[5:0]
SETCNTO[4:0]
OUT
OUT
OUT
Row count output.
Column count output.
Set count output.
Multiplex/Line Overhead Interface Signals
M0M1_ENABLEI
IN
IN
M0M1_ERRCNT data bus validation signal (one-cycle).
M0M1_ERRCNT[10:0]
M0M1 error count.
AIS_P Generation Signals
LOSF_ALL
IN
Global loss of frame or loss of signal alarm causing AIS_L
insertion.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
