VSC6134
Datasheet
Table 5.
Overhead Bytes to Be Inserted
Address
Byte-1
A1
Byte-2
A2
Byte-3
J0
0
1
2
3
4
5
6
7
B1
E1
F1
D1
D2
D3
B2
K1
K2
D4
D5
D6
D7
D8
D9
D10
S1
D11
M0/M1
D12
E2
The overhead insertion block I/O is shown in the following table.
Table 6.
SONET/SDH Overhead Insertion Block I/O
Name
Direction
Function
RESETN
IN
IN
IN
IN
IN
IN
IN
IN
Active low reset.
155 MHz system clock.
CLK
D90RESETN
D90CLK
Active low reset (622/360 domain).
1.728 MHz clock.
Row count.
ROWCNT[3:0]
COLCNT[6:0]
SETCNT[4:0]
DATAI[63:0]
Column count.
Set count.
155 Mbps input data bus. RX_DATAI is clocked in on the rising edge of
CLK. Bit 63 is the MSB.
OHI_EN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Signal from MPU to indicate bypass mode (no overhead insertion).
Signal from MPU to enable J0 insertion.
J0_ENABLE
E1_ENABLE
F1_ENABLE
D1_3_ENABLE
K1K2_ENABLE
D4_12_ENABLE
S1_ENABLE
E2_ENABLE
CLK_INVERT
Signal from MPU to enable E1 insertion.
Signal from MPU to enable F1 insertion.
Signal from MPU to enable D1, D2, D3 insertion.
Signal from MPU to enable K1, K2 insertion.
Signal from MPU to enable D4 to D12 insertion.
Signal from MPU to enable S1 insertion.
Signal from MPU to enable E2 insertion.
Signal from MPU to select negative edge CLK for input
AD/DRTXSDHOHD latches.
ROWCNTO[3:0]
OUT
Row count.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
