VSC6134
Datasheet
2.3
Tx Transport Overhead Insertion Block
The 19 transport overhead bytes are received using the transport input interface and inserted into the
Tx path data stream. The serial interface consists of the following three signals:
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AD/DRTXSDHOCLK
AD/DRTXSDHOHFS
AD/DRTXSDHOHD
The block features include:
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Supporting only one mode (mode0 has 19 bytes).
FPGA serial interface with clock speed = 1.728 MHz.
If the row and column are jumped, then it self-terminates and restarts the request.
Inserting each of the following overhead bytes is controlled by the microprocessor unit:
D1 to D12, E1, E2, F1, J0, K1, K2, S1.
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The Tx transport overhead insertion block can be enabled or disabled by the microprocessor unit.
2.3.1
Tx Overhead Insertion Port Timing
The Tx overhead insertion port timing is shown in the following figure. The AD/DRTXSDHOHFS is
the 1.728-MHz (1/360th of the 622-MHz clock rate) clock output. AD/DRTXSDHOHFS is an output
signal, generated from the rising edge of the 1.728-MHz clock. Incoming data from FPGA is expected
one clock after sending out AD/DRTXSDHOHFS. It takes 152 1.728-MHz clocks to receive all
19 bytes from FPGA. The data input order follows the SONET frame order in which the overhead bytes
are transmitted.
Figure 10. Tx Overhead Insertion Port Timing
AD/DRTXSDHOHCLK
AD/DRTXSDHOHFS
First Data
of Frame
AD/DRTXSDHOHD
The following table shows the 19 overhead bytes that are inserted into the Tx path data stream. The
shaded bytes in the table are not received from the interface and are not inserted into the Tx path data
stream. These bytes cannot be inserted from the FPGA interface.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
