VSC6134
Datasheet
(register 0x01B)= 1 (see Figure 22, page 115). In this mode of operation, the device’s phase frequency
discriminator circuit is used to achieve phase lock with the local 19.44-MHz reference.
Figure 24. RLL Implementation
19.44 MHz (from RXCLK1DIV pin)
PFD
Write Pointer
Read Pointer
RLL
Controller
1/4
VCO_MODE
VSC6134
RLLDNx
RLLUPx
TXCLKSRC1
VCXO
LPFA
2.8.8
FEC Decoder Register Information
For information about the FEC decoder registers, see “FEC Decoder Registers,” page 275.
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VMDS-10185 Revision 4.0
July 2006