VSC6134
Datasheet
Figure 23. RLL Block Schematic
Write Pointer
Read Pointer
RLL UPx Pulses
RLL DNx Pulses
UP
RLL Controller
FSM
DN
155.52MHz
Programmable
Divider
CLK_DIV[2:0]
In the normal mode of operation, the RLL FSM controls the generation of UP and DN pulses according
to the finite state machine described in this section.
The frequency of UP/DN pulses generated by the RLL control block is programmed by CLK_DIV[2:0].
The initial charge interval for charging the capacitor in the external low-pass filter begins on the rising
edge of the ACT_START bit, which starts the RLL controller FSM. Note that it is necessary to initiate
the charge interval after the drop FEC frame aligner goes into frame alignment for the first time. This is
because the clock crossing FIFO does not begin operation until the first frame alignment is achieved and
if no frames arrive for a long duration (depending on the size of the capacitor and the rate of leakage),
the initial charge of the capacitor is lost.
The interrupt status bit RLL_JUSS, and its associated interrupt mask bit RLL_JUSM, are used to
indicate that eight accumulated negative or positive justifications occurred in the OPU mapped
CBR10G payload (PJO minus NJO equals 8). The status bit is cleared on read or on write, depending
on the microprocessor configuration bit CLR_RD_WRN.
The two bits, RLL_WIN_CONVS and RLL_BP_CONVS, can be used as an RLL lock indication when
both are set to 1. The window is the count of up or down pulses that are generated by the RLL controller
on each pulse burst.
The interrupt status bit RLL_WIN_CONVS, and its associated interrupt mask bit RLL_WIN_CONVM,
is used to indicate window size convergence (window size < 2× the preset minimum window size). The
status bit is cleared on read or on write, depending on the microprocessor configuration bit
CLR_RD_WRN.
The interrupt status bit RLL_BP_CONVS, and its associated interrupt mask bit RLL_BP_CONVM, are
used to indicate beat period convergence (beat period ≥ the preset maximum beat period). The status bit
is cleared on read or on write, depending on the microprocessor configuration bit CLR_RD_WRN.
PFD - Phase Frequency Discriminator for Asychronous Mapping During LOS
During a loss of signal in the Asynchronous Demapping mode, the clock TXCLK1 must be locked to a
local, stable reference source of 19.44 MHz that is provided using pin RXCLK1DIV. This mode is also
called a Holdover mode and is enabled when drop path DROP_RX_CLOCK_SELECT
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
