VSC6134
Datasheet
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EFEC2_ERR_UPR and EFEC2_ERR_LWR: Count of correctable bit errors (ones and zeros) from
decoder 2.
EFEC1_ERR_UPR and EFEC1_ERR_LWR: Count of correctable bit errors (ones and zeros) from
decoder 1.
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EFEC4_UCW_UPR and EFEC4_UCW_LWR: Count of uncorrectable codewords from decoder 4.
EFEC3_UCW_UPR and EFEC3_UCW_LWR: Count of uncorrectable codewords from decoder 3.
EFEC2_UCW_UPR and EFEC2_UCW_LWR: Count of uncorrectable codewords from decoder 2.
EFEC1_UCW_UPR and EFEC1_UCW_LWR: Count of uncorrectable codewords from decoder 1.
Note that the enhanced FEC decoder count of 0 and 1 errors is statistical and not an exact count.
In Standard FEC mode (FEC_MODE_D = 0), the following 32-bit on-chip counters track various
errors:
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TOTAL_StFEC_ERR_UPR and TOTAL_StFEC_ERR_LWR: Count of correctable bit errors, ones
and zeros.
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StFEC_ZERO_ERR_UPR and StFEC_ZERO_ERR_LWR: Count of 0 errors, that is, a 0 is
transmitted, a 1 is received and corrected to a 0. (Note that this definition is the opposite of the
EFEC mode definition.)
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StFEC_ONE_ERR_UPR and StFEC_ONE_ERR_LWR: Count of 1 errors, that is, a 1 is
transmitted, a 0 is received and corrected to a 1. (Note that this definition is the opposite of the
EFEC mode definition.)
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TOTAL_StFEC_UCW_UPR and TOTAL_StFEC_UCW_LWR: Count of uncorrectable
codewords.
TOTAL_StFEC_SYM_ERR_UPR and TOTAL_StFEC_SYM_ERR_LWR: Count of symbol, that
is, byte errors.
The standard FEC decoder provides additional three bit pattern error statistics:
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LATE_TX_ERR_UPR and LATE_TX_ERR_LWR: Count of errors where the 0 to 1 or 1 to 0
transition comes late. (This means when 011 is transmitted, 001 is received and corrected to 011; or
100 is transmitted, 110 is received and corrected to 100. The corrected bits are in bold and the left-
most bit is received first.) Note that 011100 increments the count by 2.
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EARLY_TX_ERR_UPR and EARLY_TX_ERR_LWR: Count of errors where the 0 to 1 or 1 to 0
transition comes early. (This means when 001 is transmitted, 011 is received and corrected to 001;
or 110 is transmitted, 100 is received and corrected to 110. The corrected bits are in bold and the
left-most bit is received first.) Note that 001110 increments the count by 2.
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SRND_OPP_ERR_UPR and SRND_OPP_ERR_LWR: Count of errors with opposite surroundings
of ones or zero s. (This means when 101 is transmitted, 111 is received and corrected to 101; or 010
is transmitted, 000 is received and corrected to 010. The corrected bits are in bold.)
SRND_SAME_ERR_UPR and SRND_SAME_ERR_LWR: Count of errors with same
surroundings of ones or zeros. (This means when 111 is transmitted, 101 is received and corrected
to 111; or 000 is transmitted, 010 is received and corrected to 000. The corrected bits are in bold.)
Note that the standard FEC decoder three bit pattern errors are statistical and not an exact count. In the
64-bit words used internally, bits 0 and 63 are excluded from the three bit pattern errors.
Once every second, the error counts transfer to a set of duplicate cache registers for microprocessor read
access. Depending on the microprocessor configuration bit SAT_ROLLOVERN, the accumulators
either clear (SAT_ROLLOVERN = 1) or retain their value (SAT_ROLLOVERN = 0) when the count
transfers.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
