VSC6134
Datasheet
Table 48. Clock Crossing Buffer Modes (continued)
Configuration Bits
FIFO_MODE
FECDEC_MODE
[1:0](1)
Mode
FEC_MODE_D(1)
[1:0]
STUFF_DIS
DROP_ASYNC(1)
RSFEC (with OTU stuff bytes)
to Asynchronous
0
00
00
0
1
SDH/SONET/Transparent(1)
1
FEC Bypass
10
0
(Sonet/SDH pass through)(1)
1. This mode or function is valid in the drop path clock crossing FIFO only.
2.8.7.1
General Operation
The read and write pointers are reset to 0 on device reset and after every new frame alignment (new
frame alignment has no effect in the FEC bypass mode). However, the pointers increment normally
during the OOF condition.
2.8.7.2
FIFO Spill Detection
The clock crossing FIFO has a spill detector circuit that monitors its read and write pointers for
overflow and underflow conditions. A spill detection may also cause a new frame alignment in the
upstream frame aligner (on the device) to occur, depending on how the three configuration registers in
the Drop Decoder Configuration registers are programmed. The indication of a spill is reported in the
Drop Decoder Status register DROP_FIFO_SPILL and its interrupt can be masked with
DROP_FIFO_SPILLM. If an NFA or pointer reset is to be asserted automatically upon spill detection,
AUTO_NFA_FIFOSPILL should be set high.
To choose whether NFA or a FIFO pointer reset should be asserted, use NFA_FPRN as follows: If
AUTO_NFA_FIFOSPILL is high and NFA_FPRN is high, then an NFA is forced when a spill detection
occurs. When AUTO_NFA_FIFOSPILL is high and NFA_FPRN is low, then a FIFO pointer reset is
asserted when a spill detection occurs. If AUTO_NFA_FIFOSPILL is low, neither an NFA nor a FIFO
pointer reset is asserted when a spill is detected.
One other configuration register (FIFOSPILL_NFAONLOCK) is used to determine whether the device
must be in PLL/RLL lock before a spill detection forces NFA, or a FIFO pointer reset is asserted. If
FIFOSPILL_NFAONLOCK is high and AUTO_NFA_FIFOSPILL is high, an NFA or FIFO pointer
reset is only asserted on spill detection if the device is in PLL lock for synchronous mapping or RLL
lock for asynchronous mapping. If FIFOSPILL_NFAONLOCK is low, then NFA or FIFO pointer reset
is asserted any time AUTO_NFA_FIFOSPILL is high and a spill is detected.
Upon reset, the RAM contents are forced to a known value by writing them to all zeros.
2.8.7.3
Asynchronous Demapping
The drop-path clock crossing FIFO is capable of demapping an asynchronously mapped CBR10G
payload (for example, SONET/SDH). Based upon the rate of received data, a rate locked loop circuit
can be implemented to extract a payload clock.
The asynchronous demapping mode is enabled when DROP_ASYNC = 1. In this mode justifications
are recognized and performed by monitoring the JC bytes of the DWOH before data is written into the
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
