VSC6134
Datasheet
2.8.6
Muxes
Two multiplexers are used in the FEC decoder block for configuring the decoder in various modes.
Mux 1
Two top-level microprocessor configuration register bits, FECDEC_MODE[1:0], are used to select
various modes as shown in the following table.
Table 47. FEC Decoder Modes
FECDEC_MODE[1:0]
Mode Description
00
01
10
11
Normal mode where data is decoded, corrected, and monitored for errors.
Data is decoded and monitored for corrected errors, but is not corrected.
FEC decoder is completely bypassed (for SONET/SDH pass through applications).
Reserved.
Mux 2
In the decoder to encoder loopback mode (that is, ADD_FIFO_MODE[1:0] = 01), Mux 2 is used to
bypass the decoder clock crossing buffer (the encoder clock crossing buffer is used to synchronize data
in the FEC transmit and receive clock domains).
2.8.7
Clock Crossing Buffer
The clock crossing buffer, as shown in the following table, consists of a 48-word × 64-bit two-port
register array. For more information, see “Operational Modes,” page 152.
Table 48. Clock Crossing Buffer Modes
Configuration Bits
FIFO_MODE
[1:0]
FECDEC_MODE
[1:0](1)
Mode
FEC_MODE_D(1)
STUFF_DIS
DROP_ASYNC(1)
EFEC (with OTU stuff bytes) to
SDH /SONET/Transparent(1)
1
00
00
0
0
EFEC (without OTU stuff
bytes) to
1
00
00
1
0
SDH/SONET/Transparent(1)
EFEC to Pass Through OTU(1)
1
1
11
00
00
00
0
0
0
1
EFEC (with OTU stuff bytes) to
Asynchronous SDH
/SONET/Transparent(1)
RSFEC (with OTU stuff bytes)
to SDH /SONET/Transparent
0
0
00
00
00
00
0
1
0
0
RSFEC (without OTU stuff
bytes) to SDH
/SONET/Transparent
RSFEC to Pass Through OTU
0
11
00
0
0
113 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
